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Freescale Semiconductor,Order this document from Analog Marketing Inc.
Rev. 2.5, 11/2002
Switch Mode Power Supply with Multiple Linear Regulators and High Speed CAN Transceiver
The 33394 is a multi-output power supply integrated circuit with high speed CAN transceiver. The IC incorporates a switching pre-regulator operating over a wide input voltage range from +4.0V to +26.5V (with transients up to 45V). The switching regulator has an internal 3.0A current limit and runs in both buck mode or boost mode to always supply a pre-regulated output followed by Low Drop Out (LDO) regulators: VDDH / 5.0V @ 400mA; VDD3_3 / 3.3V @ 120mA; VDDL / 2.6V (User scalable between 3.3V - 1.25V) @ 400mA typically, using an external NPN pass transistor. The Keep Alive regulator VKAM (scalable) @ 50mA; FLASH memory programming voltage VPP / 5.0V or 3.3V @ 150mA; three sensor supply outputs VREF(1,2,3) / 5.0V (tracking VDDH) @ 100mA each; and a switched battery output (VSEN) to supply 125mA clamped to 17V. Additional features include Active Reset circuitry watching VDDH, VDD3_3, VDDL and VKAM, user selectable Hardware Reset Timer (HRT), Power Sequencing circuitry guarantees the core supply voltages never exceed their limits or polarities during system power up and power down. A high speed CAN transceiver physical layer interfaces between the microcontroller CMOS outputs and differential bus lines. The CAN driver is short circuit protected and tolerant of loss of battery or ground conditions. 33394 is designed specifically to meet the needs of modules, which use the MPC565 microcontroller, though it will also support others from the MPC5XX family of Motorola microcontrollers. Features: * Wide operating input voltage range: +4.0V to +26.5V (+45V transient).
33394
MULTI-OUTPUT POWER SUPPLY
SEMICONDUCTOR TECHNICAL DATA
Freescale Semiconductor, Inc...
44-Lead HSOP DH SUFFIX CASE 1291
44-Lead QFN FC SUFFIX CASE 1310 (BOTTOM VIEW)
* * * * * *
Provides all regulated voltages for MPC5XX MCUs and other ECU's logic and analog functions. Accurate power up/down sequencing. Provides necessary MCU support monitoring and fail-safe support. Provides three 5.0 V buffer supplies for internal & external (short-circuit protected) sensors. Includes step-down/step-up switching regulator to provide supply voltages during different battery conditions. Interfaces Directly to Standard 5.0V I/O for CMOS Microprocessors by means of Serial Peripheral Interface. PIN CONNECTIONS
INV VCOMP VPRE VPRE_S VDDH VREF2 VREF3 DO SCLK DI CS VBAT VBAT KA_VBAT VIGN VKAM /SLEEP VKAM_FB HRT VSEN CANH REGON CANL WAKEUP GND VREF1 CANTXD VPP_EN CANRXD VPP /PORESET VDD3_3 /HRESET VDD3_3FB /PRERESET VDDL_X VDDL_FB VDDL_B VDDL_FB /PRERESET /HRESET /PORESET CANRXD CANTXD 1 SW1 SW1 SW1 BOOT SW2G GND INV VCOMP VPRE VPRE_S VDDH VREF2 VREF3 DO SCLK DI CS /SLEEP HRT CANH CANL GND
54-Lead SOICW-EP DWB SUFFIX CASE 1377
PIN CONNECTIONS
GND CANL CANH HRT /SLEEP N/C CS DI SCLK DO N/C VREF3 VREF2 VDDH VPRE_S VPRE VCOMP INV GND SW2G BOOT N/C SW1 SW1 SW1 SW1 SW1 1 CANTXD CANRXD /PORESET /HRESET /PRERESET N/C VDDL_FB VDDL_B VDDL_X VDD3_3FB VDD3_3 VPP VPP_EN VREF1 WAKEUP REGON VSEN VKAM_FB VKAM VIGN N/C KA_VBAT VBAT VBAT VBAT VBAT VBAT
GND SW2G BOOT SW1 SW1 SW1 VBAT VBAT KA_VBAT VIGN VKAM
1
SOICW
QFN
HSOP
This document contains information on a new product. Specifications and information herein are subject to change without notice.
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VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B
TOP VIEW
1
Freescale Semiconductor, Inc. 33394
To Q3 Dp1 + - KA_VBAT 3 ON Control OFF 10 nF 2.6 V VKAM VKAM Keep-Alive Adj. Volt. 60 mA I-Lim 4.7 k VIGN 4 Lf1 6.8
Figure 1. 33394DH - Simplified Block Diagram and Typical Application
VBAT SW1 42-44 Oscillator Feed Forward Ramp Generator Cb 100 nF Buck Control Logic Boost + - 40 k + - - + Vbg High-Side Drive Low-Side Drive BOOT 41 SW2G 40 39 GND Q1
mH +
L1 47
mH
D2 C1 100
VPRE 5.6 V
+
Dp2
Cf1 10
mF
1, 2 Cf2 100
mF
mF
+
D1
MTD20N03HDL
+
10 nF 22
22 k
5
Freescale Semiconductor, Inc...
mF
VKAM_FB 20 k 6
INV 38
Cc3 3.3 nF Rc2 100 k Cc2 Rc3 430R
11.7 k 100 pF
Cc1
VSEN 7 REGON 8 WAKEUP 9 5.0 V VREF1
VSEN VBAT Volt. 125 mA T-Lim, I-Lim CANRXD Sleep VREF1 5.0 V 100 mA LDO T-Lim, I-Lim CAN Wakeup Logic Vbg VPP 5.0 V/3.3 V 150 mA LDO T-Lim, I-Lim Band Gap Reference VREF2 5.0 V 100 mA LDO T-Lim, I-Lim VDDH 5.0 V 400 mA LDO T-Lim, I-Lim Enable
VCOMP 1.0 nF 37 36 35 VPRE VPRE_S
VDDH 34 47
5.0 V
+
10 nF 1.0
10
mF
11
mF
+
10 nF
VPP_EN 5.0 V/3.3 V VPP
VREF2 33 1.0
5.0 V
+
10 nF
12
47 VDD3_3 13 VDD3_FB
mF
mF
+
10 nF
3.3 V
10 nF 47
mF
+
14 VQ3
VDD3_3 3.3 V 120 mA LDO, Pass T-Lim, I-Lim
Standby Control
VREF3 5.0 V 100 mA LDO T-Lim, I-Lim
VREF3 32 1.0
5.0 V
VPRE
mF
+
10 nF
Q2 MJD31C VDDL 2.6 V
Q3 MJD31C
VDDL_B VDDL Drive Adj. Volt. VDDL_X 40 mA 16 VDDL_FB Dual Pass T-Lim 17 15 18 Reset Detection VDDH, VDD3_3, VDDL
16 Bit SPI Control Fault Rep.
31 30 29 28
DO SCLK DI CS VDDH 5.0 V
+
10 nF 47
mF
110R /PRERESET 100R
Sleep 27 High-Speed CAN Transceiver HRT POR Timer 26
/SLEEP 47 k 1.0
/HRESET 19 /PORESET 20 10 k 10 k 10 k
Notes: Notes: Notes: Notes:
CANH CANTXD 120 R GND 1. In this configuration the device can operate with a minimum input voltage VBAT of 4.0 V (voltage at 33394 VBAT pins). 2.VDDL and VKAM are adjustable to support current microprocessor technology (1.25 V to 3.3 V) by means of an external resistor divider. 3. When the 33394 CAN transceiver is not used, CANL and CANH pins can be shorted together. 4. Dp1 = reverse battery protection diode. Dp2 = load dump protection diode. Dp1, Dp2 can be ommitted in those applications which do not require such protection.
VKAM 2.6 V
21 CANRXD
22
23
24
25 CANL
mF
2
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Freescale Semiconductor, Inc. 33394
PIN FUNCTION DESCRIPTION (44-HSOP Package)
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 NAME VBAT VBAT KA_VBAT VIGN VKAM VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB /PRERESET /HRESET /PORESET CANRXD CANTXD GND CANL CANH HRT /SLEEP CS DI SCLK DO VREF3 VREF2 VDDH VPRE_S VPRE VCOMP INV GND SW2G BOOT SW1 SW1 SW1 DESCRIPTION Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Keep alive supply (with internal protection diode) Turn-On control through ignition switch (with internal protection diode) VDDL tracking Keep Alive Memory (Standby) supply VKAM output feedback Switched battery output Regulator "Hold On" input CAN wake up event output VDDH tracking linear regulator 1 VPP enable 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL optional external pass transistor base drive, operating in Boost Mode only VDDL external pass transistor base drive VDDL output feedback Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) Open drain / HRESET (Hardware Reset) output Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. CAN receive data (DOUT) CAN transmit data (DIN) Ground CAN differential bus drive low line CAN differential bus drive high line Hardware Reset Timer pin (programmed with external capacitor and resistor) Sleep Mode & Power Down control SPI chip select SPI serial data in SPI clock input SPI serial data out VDDH tracking linear regulator 3 VDDH tracking linear regulator 2 5.0 V regulated supply output Switching pre-regulator output sense Switching pre-regulator output Switching pre-regulator compensation (error amplifier output) Switching pre-regulator error amplifier inverting input Ground External power switch (MOSFET) gate drive -- Boost regulator Bootstrap capacitor Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET)
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12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
NOTE: The exposed pad of the 44 HSOP package is electrically and thermally connected with the IC ground.
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PIN FUNCTION DESCRIPTION (44-QFN Package)
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 NAME GND SW2G BOOT SW1 SW1 SW1 VBAT VBAT KA_VBAT VIGN VKAM VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB /PRERESET /HRESET /PORESET CANRXD CANTXD GND CANL CANH HRT /SLEEP CS DI SCLK DO VREF3 VREF2 VDDH VPRE_S VPRE VCOMP INV Ground External power switch (MOSFET) gate drive -- Boost Reg. Bootstrap capacitor Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Keep alive battery supply (with internal protection diode) Turn on control through ignition switch (with internal protection diode) VDDL tracking Keep Alive Memory (Standby) supply VKAM output feedback Switched battery output Regulator "Hold On" input CAN wake up event output VDDH tracking linear regulator 1 VPP enable 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL optional external pass transistor base drive, operating in Boost Mode only VDDL external pass transistor base drive VDDL output feedback Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) Open drain / HRESET (Hardware Reset) output Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. CAN receive data (DOUT) CAN transmit data (DIN) Ground CAN differential bus drive low line CAN differential bus drive high line Hardware Reset Timer pin (programmed with external capacitor and resistor) Sleep Mode & Power Down control SPI chip select SPI serial data in SPI clock input SPI serial data out VDDH tracking linear regulator 3 VDDH tracking linear regulator 2 5.0 V regulated supply output Switching pre-regulator output sense Switching pre-regulator output Switching pre-regulator compensation (error amplifier output) Switching pre-regulator error amplifier inverting input DESCRIPTION
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12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
NOTE: The exposed pad of the 44 QFN package is electrically and thermally connected with the IC ground.
4
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Freescale Semiconductor, Inc. 33394
PIN FUNCTION DESCRIPTION (54 SOICW-EP Package)
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME GND CANL CANH HRT /SLEEP N/C CS DI SCLK DO N/C VREF3 VREF2 VDDH VPRE_S VPRE VCOMP INV GND SW2G BOOT SW1 SW1 SW1 SW1 SW1 VBAT VBAT VBAT VBAT VBAT KA_VBAT N/C VIGN VKAM VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB N/C /PRERESET /HRESET /PORESET CANRXD CANTXD Ground CAN differential bus drive low line CAN differential bus drive high line Hardware Reset Timer pin (programmed with external capacitor and resistor) Sleep Mode & Power Down control No Connect SPI chip select SPI serial data in SPI clock input SPI serial data out No Connect VDDH tracking linear regulator 3 VDDH tracking linear regulator 2 5.0 V regulated supply output Switching pre-regulator output sense Switching pre-regulator output Switching pre-regulator compensation (error amplifier output) Switching pre-regulator error amplifier inverting input Ground External power switch (MOSFET) gate drive -- Boost regulator Bootstrap capacitor Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Source of the internal power switch (n-channel MOSFET) Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Battery supply to IC (external reverse battery protection needed in some applications) Keep alive supply (with internal protection diode) No Connect Turn-On control through ignition switch (with internal protection diode) VDDL tracking Keep Alive Memory (Standby) supply VKAM output feedback Switched battery output Regulator "Hold On" input CAN wake up event output VDDH tracking linear regulator 1 VPP enable 5.0 V/ 3.3 V FLASH memory programming supply, tracking VDDH/VDD3_3 3.3 V regulated supply output, base drive for optional external pass transistor VDD3_3 output feedback VDDL optional external pass transistor base drive, operating in Boost Mode only VDDL external pass transistor base drive VDDL output feedback No Connect Open drain /PRERESET output, occurs 0.7 us prior to /HRESET (Hardware Reset) Open drain / HRESET (Hardware Reset) output Open drain / PORESET (Power On Reset) supervising VKAM supply to the microprocessor. CAN receive data (DOUT) CAN transmit data (DIN) DESCRIPTION
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15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
NOTE: The exposed pad of the 54 SOICW-EP package is electrically and thermally connected with the IC ground.
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1. MAXIMUM RATINGS (Maximum Ratings indicate sustained limits beyond which damage to the device may occur.
Voltage parameters are absolute voltages referenced to ground.) Parameter Supply Voltage (VBAT), Load Dump Supply Voltage (KA_VBAT, VIGN), Load Dump Supply Voltages (VDDH, VPP, VDD3_3, VDDL, VKAM) Supply Voltages (VREF1, VREF2, VREF3, VSEN) CANL, CANH (0Freescale Semiconductor, Inc...
CANTXD, CANRXD Operational Package Temperature [Ambient Temperature] Storage Temperature Power Dissipation (TA = 125_C) 44 HSOP 44 QFN 54 SOICW-EP Lead Soldering Temperature Maximum Junction Temperature RJA, Thermal Resistance, Junction to Ambient (44 HSOP) RJC, Thermal Resistance, Junction to Case (44 HSOP) RJB, Thermal Resistance, Junction to Base (44 HSOP) RJA, Thermal Resistance, Junction to Ambient (44 QFN) RJC, Thermal Resistance, Junction to Case (44 QFN) RJB, Thermal Resistance, Junction to Base (44 QFN) RJA, Thermal Resistance, Junction to Ambient (54 SOICW-EP) RJC, Thermal Resistance, Junction to Case (54 SOICW-EP) RJB, Thermal Resistance, Junction to Base (54 SOICW-EP)
_C
C C/W C/W C/W C/W C/W C/W C/W C/W C/W
1. Human body model: C = 100 pF, R = 1.5 k. 2. Machine model: C = 200 pF, R = 10 and L = 0.75 H. In case of a discharge from pin CANL to pin GND: - 100 V < CANL transient < +100 V; in case of a discharge from pin CANH to Vcc: -150 V < CANH transient < +150 V. 3. The waveforms of the applied transients is in accordance with "ISO 7637 part 1" test pulses 1, 2, 3a and 3b. 4. Maximum power dissipation at indicated junction temperature. 5. Lead soldering temperature limit is for 10 seconds maximum duration; contact Motorola Sales Office for device immersion soldering time/temperature limits. 6. Thermal resistance measured in accordance with EIA/JESD51-2. 7. Theoretical thermal resistance from the die junction to the exposed pad. 8. Thermal resistance measured in accordance with JESD51-8.
2. RECOMMENDED OPERATING CONDITIONS (All voltages are with respect to ground unless otherwise noted)
Parameter Supply Voltages (VBAT, KA_VBAT) Switching Regulator Output Current (IVPRE) VDDH Output Current VDD3_3 Output Current VDDL_B Pass Transistor Base Drive Current VPP Output Current VREF Output Current VSEN Output Current VKAM Standby Output Current (normal mode of operation) VKAM Standby Output Current (standby mode of operation) 1. See Typical Application Diagram in Figure 1. (Note 1) Value 4.0 to 26.5 0 to 1.2 0 to 400 0 to 120 0 to 40 0 to 150 0 to 100 0 to 125 0 to 60 0 to 12 Unit V A mA mA mA mA mA mA mA mA
6
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
GENERAL Start Up Voltage Power Dissipation, VBAT = 13.3 V (Buck Mode) Undervoltage Shut Down Battery Input Current, Power Down Mode, VIGN = 0 V; REGON = 0 V; IVKAM = 0 mA, VBAT = 13.3 V; Battery Voltage = 14 V Battery Input Current, Keep Alive Mode VIGN = 0; IVKAM = -10 mA Power On Current, Regulator ON with no load on VDDH, VDD3_3, VDDL, VKAM, VREF, VPP, VSEN; VBAT = 13.3 V Battery Input Current, VPRE = -1.0 A, VBAT = 4.5 V IVBAT(no load) IVBAT(4.5) IVBAT(9) IVBAT(13.3) IVBAT(18) VIH VIL RPD VIH VIL VIhys RPD VIH VIL VIhys RPD VIH VIL RPD 2.8 1.7 0.7 40 1.3 0.8 0.2 10 1.7 1.4 0.2 10 1.3 0.8 10 3.15 2.0 1.0 100 1.65 1.35 0.3 20 2.2 1.9 0.3 20 1.65 1.35 20 2.2 VBATUV IVBAT(sleep) 3.4 750 VBATstart 1.8 3.9 1000 12 27 3.0 1.5 1.2 1.1 3.4 2.3 1.5 150 2.1 1.5 0.4 50 2.6 2.2 0.4 50 2.1 1.5 50 6.2 V W V A mA mA A A A A V V A V V V A V V V A V V A
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Battery Input Current, VPRE = -1.0 A, VBAT = 9 V Battery Input Current, VPRE = -1.0 A, VBAT = 13.3 V Battery Input Current, VPRE = -1.0 A, VBAT = 18 V MODE CONTROL VIGN Input Voltage Threshold, REGON = 0 V VBAT = 13.3 V; Battery Voltage = 14 V VIGN Hysteresis VIGN Pull-Down Current, REGON = 0V VBAT = 13.3 V, Battery Voltage = 14 V, VIGN = 14 V REGON Input High Voltage Threshold REGON Input Low Voltage Threshold REGON Input Voltage Threshold Hysteresis REGON Pull-Down Current, REGON = VDDH to VIL(min) /SLEEP Input High Voltage Threshold /SLEEP Input Low Voltage Threshold /SLEEP Input Voltage Threshold Hysteresis /SLEEP Pull-Down Current, /SLEEP = VDDH to VIL(min) VPP_EN Input High Voltage Threshold VPP_EN Input Voltage Low Threshold VPP_EN Pull-Down Current, VPP_EN = VDDH to VIL(min)
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3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
BUCK CONVERTER Buck Converter Output Voltage, VBAT = 7.5V to 18V; ILOAD=500mA Buck to Boost Mode Threshold Voltage Boost to Buck Mode Threshold Voltage N-channel power MOSFET SW1 SW1 Drain-Source Breakdown Voltage SW1 Continuous Drain Current SW1 Drain-Source Current Limit SW1 Drain-Source On-Resistance; ID = 1.0 A, VBAT = 9.0 V Error Amplifier (Design Information Only) Input Offset Voltage DC Open Loop Gain Unity Gain Bandwidth Output Voltage Swing -- High Level Output Voltage Swing -- Low Level Output Source Current Output Sink Current Ramp Generator Sawtooth Peak Voltage Sawtooth Peak-to-Peak Voltage BOOST CONVERTER External Power MOSFET Gate Drive SW2G Boost Converter Output Voltage, VBAT = 4.5 V to 6.0 V SW2G Output Voltage, Power MOSFET On SW2G Source Continuous Current SW2G Sink Continuous Current (Note 1) (Note 1) (Note 1) VPRE Vg Isource Isink 200 5.9 6.0 VPRE TBD 300 400 6.6 V V mA mA (Note 1) (Note 1) VOSC VOSCp-p 3.5 3.0 V V (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) BVDSS IDSW1 IscSW1 RDS(on) VOS AVOL BW VOH VOL IOUT IOUT 20 80 1.5 4.2 0.4 1.0 200 50 -2.75 -2.5 -3.0 -3.5 300 V A A m (Note 1) (Note 1) VPRE VBATthd VBATthu 5.4 5.6 6.7 7.2 5.8 V V V
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mV dB MHz V V mA A
AC CHARACTERISTICS:
BUCK CONVERTER Oscillator Frequency SW1 Switch Turn-ON Time SW1 Switch Turn-OFF Time SW2G Switch Turn-ON Time, Cgate = pF SW2G Switch Turn-OFF Time, Cgate = pF OFF Time Duty cycle NOTE: 1. Guaranteed by design but not production tested. (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) (Note 1) Freq tT-ON tT-OFF tT-ON tT-OFF tOFF d 180 200 TBD TBD TBD TBD 1.25 75 220 kHz ns ns ns ns s %
8
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
VDDH VDDH Output Voltage, IVDDH = -400 mA; VDDH Load Regulation, VBAT = 13.3 V; IVDDH = 0 to -400 mA; VDDH Line Regulation, VBAT = 4.0 V to 26.5 V; IVDDH = -400 mA; VDDH Drop Out Voltage, VPRE - VDDH, IVDDH = -400 mA; Decrease VBAT until Resets asserted VDDH Output Current, VBAT = 4.0 V to 26.5 V VDDH Short Circuit Current, VDDH = 0 V VDDH Maximum Allowed Feedback Current (Power Up Sequence Guaranteed) (Note 1) (Note 2) VVDDH_HRST TSDIS TSHYS VDD3_3 LoadRgVDD3 LineRgVDD3 VDOV IVDD3_3 ISC (Note 1) (Note 2) VVDD3_HRST (Note 1) (Note 1) TSDIS TSHYS VDDLREF LoadRgVDDL LineRgVDDL VDOV (Note 1) (Note 3) VVDDL_HRST VDDLREF IVDDL_B IscVDDL_B IVDDL_B IscVDDL_X -100 -100 -40 -45 2.0 -40 -45 0.5 0.5 150 5.0 1.242 -1.6 -0.8 1.267 -320 -120 -130 135 3.1 190 20 1.292 0 0.8 1.3 VDDL -5% 0.187 0.5 150 5.0 3.21 -40 -20 3.3 VDDH LoadRgVDDH LineRgVDDH VDOV IVDDH ISC -750 -400 -440 135 4.8 190 20 3.36 40 20 2.04 4.9 -40 -20 5.0 5.1 40 20 450 V mV mV mV mA mA A V C C V mV mV V mA mA A V C C V % % V V V mA mA mA mA A
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VDDH Reset Voltage, Range of VDDH where Resets must remain asserted Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis VDD3_3 VDD3_3 Output Voltage, IVDD3_3 = -120 mA; VDD3_3 Load Regulation, VBAT = 13.3 V; IVDD3_3 = 0 to -120 mA VDD3_3 Line Regulation, VBAT = 4.0V to 26.5V; IVDD3_3 = -120mA VDD3_3 Drop Out Voltage, VPRE - VDD3_3 IVDD3_3 = -120 mA; Decrease VBAT until Resets asserted VDD3_3 Output Current, VBAT = 4.0 V to 26.5 V VDD3_3 Short Circuit Current, VDD3_3 = 0 V VDD3_3 Maximum Allowed Feedback Current (Power Up Sequence Guaranteed) VDD3_3 Reset Voltage Range of VDD3_3 where Resets must remain asserted Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis VDDL VDDL Feedback Reference Voltage, pin VDDL_FB IVDDL_B = 0 to -40 mA VDDL Load Regulation, VBAT = 13.3 V; IVDDL_B = 0 to -40 mA VDDL Line Regulation VBAT = 4.0 V to 26.5 V; IVDDL_B = -40 mA VDDL Drop Out Voltage, VPRE - VDDL IVDDL = -400 mA; VBAT decreases until Resets asserted VDDL Reset Voltage, Range of VDDL where Resets must remain asserted VDDL Susceptibility to Feeding Back (Power Up Sequence Guaranteed) VDDL_B Drive Output Current, VBAT = 7.5V to 26.5V VDDL_B Drive Short Circuit Current VDDL_B = 0V, VBAT = 7.5V to 26.5V VDDL_X Drive Output Current, VBAT = 4.0 V to 6 V VDDL_X Drive Short Circuit Current, VDDL_X = 0V, VBAT = 4.0V to 6V (Note 1) (Note 1)
VDDL Feedback VDDL_FB Input Current, VDDL_FB = 5.0 V IVDDL_FB 0 NOTE: 1. Guaranteed by design but not production tested. 2. Maximum allowed current flowing back into the regulator output. 3. Voltage fed back into the VDDL output, which still guaranties proper Power Up sequencing.
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
VKAM VKAM Feedback Reference Voltage, pin VKAM_FB Normal Mode (switcher running), IVKAM = 0 to -50mA VKAM Load Regulation, VBAT = 13.3 V; IVKAM = -0 to -50 mA VKAM Line Regulation, VBAT = 4.0 V to 26.5 V; IVKAM = -50 mA VKAM Tracking to VDDL Voltage, VDDL - VKAM VBAT = 4.0 V to 26.5 V; IVKAM = 0 to -50 mA, IVDDL = 0 to -400mA VKAM Feedback Voltage -- Power Down Mode 3.0 V Battery Voltage 26.5 V, IVKAM = -12 mA VKAM Reset Voltage (/PORESET) Range of VKAM where Resets must remain asserted VKAMREF LoadRgVKAM LineRgVKAM VTVKAM VKAM VVKAM_HRST IVKAM IVKAM(sleep) ISC IVKAM_FB -140 0 22 VPP5 VPP3 LoadRgVPP LineRgVPP VTVPP 4.86 3.22 -0.8 -0.4 -0.8 5.0 3.3 1.242 -1.6 -0.8 -1.6 0.675 0.5 -50 -12 -50 2.0 100 5.12 3.38 0.8 0.4 0.8 VKAM -5% 1.267 1.292 0 0.8 0.8 V % % % V V mA mA mA A F V V % % %
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VKAM Output Current (Normal Mode), VBAT = 4.0 V to 26.5 V VKAM Output Current (Sleep Mode and when VBAT 4.0 V) VKAM Short Circuit Current, VKAM = 0 V VKAM Feedback VKAM_FB Input Current, VKAM_FB = 5.0 V VKAM Output Capacitance Required, Capacitor Initial Tolerance 10% VPP VPP 5.0V Output Voltage (Default), IVPP = -150 mA VPP 3.3 V Output Voltage (Programmed by SPI) IVPP = -150 mA VPP Load Regulation, VBAT = 13.3 V; IVPP = 0 to -150 mA VPP Line Regulation, VBAT = 4.0 V to 26.5 V; IVPP = -150 mA VPP Tracking to VDDH Voltage, VDDH - VPP, VBAT = 4.0 V to 26.5 V; IVPP = 0 to -150 mA; IVDDH = 0 to -400 mA VPP Drop Out Voltage, VPRE -- VPP (VPP set to default 5.0V) IVPP = -150 mA; Decrease VBAT until VPP is out of specification (less than 4.86 V) VPP Output Current, VBAT = 4.0 V to 26.5 V VPP Short Circuit Current, VPP = 0 V Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis NOTE: 1. Guaranteed by design but not production tested. (Note 1) (Note 1)
VDOV
0.4
V
IVPP ISC TSDIS TSHYS -360 150 5.0
-150 -165 190 20
mA mA C C
10
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
VREF1, 2, 3 VREF Output Voltage, IVREF = -100 mA VREF Load Regulation, VBAT = 13.3 V; IVREF = 0 to -100 mA VREF Line Regulation, VBAT = 4.0 V to 26.5 V; IVREF = -100 mA VREF Tracking to VDDH Voltage, VDDH - VREF, VBAT = 4.0 V to 26.5 V, IVREF = 0 to -100 mA; IVDDH = 0 to -400 mA VREF Drop Out Voltage, VPRE-VREF IVREF = -100 mA; Decrease VBAT until VREF is out of specification (less than 4.86 V) VREF Output Current, VBAT = 4.0 V to 26.5 V VREF LoadRgVREF LineRgVREF VTVREF 4.86 -40 -20 -40 5.0 5.12 40 20 20 V mV mV mV
VDOV
0.4
V
IVREF ISC IstbVREF ILKVREF (Note 1) (Note 1) TSDIS TSHYS VSENsat VSENlimit IscVSEN IstbVSEN ILKVSEN (Note 1) (Note 1) TSDIS TSHYS 150 5.0 16 -290 -2.0 150 5.0 -260
-100 -110 40
mA mA mA mA 190 20 0.2 C C V V mA mA A C C
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VREF Short Circuit Current, VREF = -2.0 V VREF Short to Battery Load Current, VBAT = 18 V, VREF = 18 V VREF Leakage Current, VREF disabled, VREF = -2.0 V Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis VSEN VSEN Saturation Voltage, IVSEN = 0 to -125 mA, VBAT= 8 to 16 V VSEN Output Voltage Limit, IVSEN = 0 to -125mA, VBAT= 16 to 26.5V VSEN Short Circuit Current, VSEN = -2.0 V VSEN Short to Battery Load Current, VBAT = 18 V, VSEN = 18 V VSEN Leakage Current, VSEN disabled, VSEN = -2.0 V Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis NOTE: 1. Guaranteed by design but not production tested.
17
21 -140 40 200 190 20
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
SUPERVISORY OUTPUTS Reset Voltage Thresholds /HRESET to follow /PRERESET by 0.7 s VDDH Reset Upper Threshold Voltage VDDH Reset Lower Threshold Voltage VDD3_3 Reset Upper Threshold Voltage VDD3_3 Reset Lower Threshold Voltage VDDL Reset Upper Threshold Voltage VDDL Reset Lower Threshold Voltage /PORESET Voltage Threshold VKAM Reset Upper Threshold Voltage (Notes 2, 5) (Notes 2, 5) 1.2 7.0 1.0 0.5 15 VDDH-0.8 0.4 2.49 2.53 2.57 1.0 5.0 0.4 1.35 V V V mA V A V V V mA A V (Note 1) (Note 1) (Note 1) (Note 1) (Notes 1, 4) (Notes 1, 4) 1.2 3.17 1.35 4.8 3.43 5.2 V V V V V V
Freescale Semiconductor, Inc...
VKAM Reset Lower Threshold Voltage
/PRERESET, /HRESET, /PORESET Open Drain Maximum Voltage (Note 3) /PRERESET, /HRESET, /PORESET Open Drain Pull-Down Current, Vreset< 0.4 V /PRERESET, /HRESET, /PORESET Low-Level Output Voltage, IOL = 1.0 mA /PRERESET /HRESET /PORESET Leakage Current WAKEUP High-Level Output Voltage, IOH = -800A WAKEUP Low-Level Output Voltage, IOL = 1.6 mA HRT Voltage Threshold HRT Sink Current HRT Leakage Current HRT Saturation Voltage, HRT Current = 1 mA
AC CHARACTERISTICS:
SUPERVISORY OUTPUTS /PORESET Delay Delay time from VKAM in regulation and stable to the release of /PORESET Reset Delay Time Time from fault on VDDH, VDD3_3, VDDL or VKAM to Reset (/PORESET, /PRERESET) /HRESET Delay Time Time From /PRERESET low to /HRESET low VDDH, VDDL, VREF Power Up Sequence Max Power Up Sequence Time Dependent on Output Load Characteristics. (Note 3) NOTE: 1. VDDH, VDD3_3, VDDL regulator outputs supervised by /PRERESET and /HRESET. 2. VKAM regulator output supervised by /PORESET. 3. Guaranteed by design but not production tested. 4. Measured at the VDDL_FB pin. 5. Measured at the VKAM_FB pin. 7.0 10 15 ms
10
20
50
s
0.5 800
0.7
1.0
s s
12
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
CAN Transceiver (Bus Load CANH to CANL RL = 60 ; Vdiff = VCANH - VCANL) CAN Transceiver Supply Current (dominant), VCANTXD = 0V CAN Transceiver Supply Current (recessive), VCANTXD = VDDH Transmitter Data Input CANTXD High-Level Input Voltage Threshold (recessive), Vdiff<0.5V Low-Level Input Voltage Threshold (dominant), Vdiff>1.0V High-Level Input Current, VCANTXD = VDDH Low-Level Input Current, VCANTXD = 0V CANTXD Pull-up Current, VCANTXD = 0V to VIH(max) CANTXD Input Capacitance (Note 1) Receiver Data Output CANRXD High-Level Output Voltage VCANTXD = VDDH, ICANRXD = -0.8 mA Low-Level Output Voltage, VCANTXD = 0, ICANRXD = 1.6 mA High-Level Output Current, VCANRXD = 0.7VDDH Low-Level Output Current, VCANRXD = 0.4V BUS Lines CANH, CANL Output Voltage CANH (recessive) VCANTXD = VDDH; RL = open Output Voltage CANL (recessive) VCANTXD = VDDH; RL = open Output Current CANH (recessive) VCANTXD = VDDH; VCANH, VCANL = 2.5V Output Current CANL (recessive) VCANTXD = VDDH; VCANH, VCANL = 2.5V Output Voltage CANH (dominant), VCANTXD = 0V Output Voltage CANL (dominant), VCANTXD = 0V Differential Output Voltage (dominant) VCANH(d) - VCANL(d) VCANTXD = 0V Differential Output Voltage (recessive) VCANH(r) - VCANL(r) VCANTXD = VDDH Differential Input Common Mode Voltage Range Differential Receiver Threshold Voltage (recessive) VCANTXD = VDDH, VCANRXD < 0.4V, - 2.0V < VCM < 7.0V Differential Receiver Input Voltage Hysteresis Short Circuit Output Current CANH VCANH = - 8.0V, VCANTXD = 0V Short Circuit Output Current CANL VCANL = VBAT = 18V, VCANTXD = 0V Output Leakage Current CANH, VCANH = -18V Output Leakage Current CANHL, VCANL = -18V Input Leakage Current CANH, VCANH = 6.0V Input Leakage Current CANHL, VCANL = 6.0V NOTE: 1. Guaranteed by design but not production tested. VCANH(r) VCANL(r) IO(CANH)(r) IO(CANL)(r) VCANH(d) VCANL(d) VOdiff(d) VOdiff(r) VCM VRXDdiff(th) VIdiff(hys) ISC(CANH) ISC(CANL) -100 2.75 0.5 1.5 0 -2.0 0.5 0.10 -70 70 0.75 0.2 3.5 1.5 2.0 4.5 2.25 3.0 0.5 7.0 1.0 0.30 -200 200 2.0 2.0 2.5 2.5 3.0 3.0 100 V V A A V V V V V V V mA mA VOH VOL IOH IOL VDDH -0.8 VDDH 0.4 -800 1.6 V V A mA VIH VIL IIH IIL IPU CI(TXD) 1.4 0.8 -5 -10 -10 5 0 -15 2.0 1.4 +5 -30 -60 10 V V A A A pF IDD(CAN) IDD(CAN) 30 2.5 50 5 70 10 mA mA
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Loss of Ground -- see Figure 11. Refer to Figure 10 for loading considerations. IOLKG(CANH) IOLKG(CANL) IILKG(CANH) IILKG(CANL) -2.0 -2.0 2.0 2.0 mA mA A A
Loss of Battery -- see Figure 12. Refer to Figure 10 for loading considerations. -800 -800 800 800
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
CAN Transceiver (Continued) (Bus Load CANH to CANL RL = 60 ; Vdiff = VCANH - VCANL) CANH,CANL impedance CANH Common Mode Input Resistance CANL Common Mode Input Resistance CANH, CANL Common Mode Input Resistance Mismatch 100(RiCANH - Ri(CM)CANL )/[ (RiCANH + Ri(CM)CANL )/2] Differential Input Resistance CANH Input Capacitance, VCANTXD = VDDH CANL Input Capacitance, VCANTXD = VDDH Differential Input Capacitance, CINCANH - CINCANL, VCANTXD = VDDH (Note 1) (Note 1) (Note 1) C C Ri(CM)CANH Ri(CM)CANL Ri(CM)MCAN RI(dif) CI(CANH) CI(CANL) CI(CANdif) 5.0 5.0 -3.0 25 50 7.5 7.5 3.75 25 25 50 50 3.0 75 20 20 10 k k % k pF pF pF
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Thermal Shutdown Thermal Shutdown Junction Temperature Thermal Shutdown Hysteresis (Note 1) (Note 1) TSDIS TSHYS 150 5.0 190 20
AC CHARACTERISTICS:
CAN Transceiver Timing Characteristics See Figure 2, CANTXD = 250 kHz square wave; CANH & CANL Load RL = 60 differential. Delay CANTXD to Bus Active, CL = 3nF Delay CANTXD to Bus Inactive, CL = 10pF Delay CANTXD to CANRXD, Bus Active, CL = 3nF Delay CANTXD to CANRXD, Bus Inactive, CL = 10pF NOTE: 1. Guaranteed by design but not production tested. VDDH (5V) 0V CANH = 3.5V (Dominant bit) CANH (Recessive bit) CANL (Recessive bit) Vdiff CANL = 1.5V (Dominant bit) 2.5 V tonTXD toffTXD tonRXD toffRXD 50 80 120 190 ns ns ns ns
CANTxD
0.9 V Vdiff 0.5 V VDDH (5V) CANRxD 0.3VDDH 0V tonTxD tonRxD toffTxD toffRxD 0.7VDDH
Figure 2. CAN Delay Timing Waveform
14
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Freescale Semiconductor, Inc. 33394
3. ELECTRICAL CHARACTERISTICS (-40C TA +125C; +4.0 V VBAT +26.5 V using the 33394 typical application circuit - see Figure 1, unless otherwise noted.)
Characteristic Symbol Min. Typ. Max. Unit
DC CHARACTERISTICS:
SPI DO Output High Voltage, IOH = -100 A DO Output Low Voltage, IOL = 1.6 mA DO Tri-state Leakage Current, CS = 0 CS, SCLK, DI Input High Voltage CS, SCLK, DI Input Low Voltage CS, SCLK, DI Input Voltage Threshold Hysteresis CS, SCLK, DI Pull-Down Current, CS, SCLK, DI = VDDH to VIL(min) VOH VOL IDOLkg VIH VIL VIhys ISPI_PD -10 2.7 1.7 0.8 10 3.1 2.1 1.0 20 4.2 0.4 10 3.5 2.5 1.2 50 V V A V V V A
AC CHARACTERISTICS:
SPI
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NOTES: MPC565 QSMCM/ SPI set for CPHA = 0 & CPOL = 0. *Assumes MPC565 SCLK rise and fall times of 30 ns, DO load = 200pF - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Transfer Frequency SCLK Period Enable Lead Time Enable Lag Time SCLK High Time* SCLK Low Time* SDI Input Setup Time SDI Input Hold Time SDO Access Time SDO Disable Time SDO Output Valid Time SDO Output Hold Time Rise Time (Design Information) Fall Time (Design Information) CS Negated Time (Note 1) (Note 1) (Note 1) fop tsck tlead tlag tsckhs tsckls tsus ths ta tdis tvs tho tro tfo tcsn dc 200 105 50 70 70 16 20 - - - 0 - - 500 5.00 - - - - - - - 75 100 75 - 30 30 - MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTE: 1. Guaranteed by design but not production tested.
3
20% and 70% of Vdd typ.
14
CS
2
SCLK
4
1
5 8
DO LSB OUT
10
DATA
11
MSB OUT DON'T CARE
9
6
DI LSB IN
7
DATA
12 13
MSB IN
Figure 3. SPI Timing Diagram
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Freescale Semiconductor, Inc. 33394
4. FUNCTIONAL DESCRIPTION
The 33394 is an integrated buck regulator/linear supply specifically designed to supply power to the Motorola MPC55x/MPC56x microprocessors. A detailed functional description of the Buck Regulator, Linear Regulators, Power Up/Down Sequences, Thermal Shutdown Protection, Can Transceiver Reset Functions and Reverse Battery Function are given below. Block diagram of the 33394 is given in Figure 1. The 33394 is packaged in a 44 pin HSOP, 54 pin SOICW and the 44 pin QFN. output are brought out to enable the control loop to be externally compensated. The compensation technique is described in paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section. In order to improve line rejection, feed forward is implemented in the ramp generator. The feed forward modifies the ramp slope in proportion to the VBAT voltage in a manner to keep the loop gain constant, thus simplifying loop compensation. At startup, a soft start circuit lowers the current limit value to prevent potentially destructive in-rush current. In Boost mode, pulse-frequency modulation (PFM) control is utilized. The duty cycle is set to 75% and the switching action is stopped either by the Boost Comparator, sensing the switcher output voltage VPRE, or by the Current Limit circuit when the switching current reaches its predetermined limit value. This control method requires no external components. The selection of the control method is determined by the control logic based on the VBAT input voltage.
4.1. Input Power Source (VBAT, KA_VBAT & VIGN)
The VBAT and KA_VBAT pins are the input power source for the 33394. The VBAT pins must be externally protected from vehicle level transients greater than +45 V and reverse battery. See typical application diagram in Figure 1. The VBAT pins directly supply the pre-regulator switching power supply. All power to the linear regulators (except VKAM in the power down mode) is supplied from VBAT through the switching regulator. VKAM power is supplied through VBAT input pins and switching regulator when the 33394 is awake. When the microprocessor is in a power down mode (no VDDH or VDDL supply), the current requirement on VKAM falls to less than 12 mA. During this period the VKAM current is supplied from the reverse battery protected KA_VBAT input. The KA_VBAT supply pin is the power source to the Keep Alive Memory regulator (VKAM) in power down mode. Power is continuously supplied regardless of the state of the ignition switch (VIGN input). The KA_VBAT input is reverse battery protected but requires external load dump protection (refer to Figure 1). The VIGN pin is used as a control input to the 33394. The regulation circuits will function and draw current from VBAT when VIGN is high (active) or REGON is high (active) or on CAN bus activity (WAKEUP active). To keep the VIGN input from floating, a 10kW pull-down resistor to GND should be used. The VIGN pin has a 3.0 V threshold and 1.0 volt of hysteresis. VIGN is designed to operate up to +26.5 volt battery while providing reverse battery and +45 volt load dump protection. The input requires ESD, and transient protection. See Figure 1 for external component required.
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4.2.1. Switching Transistor (SW1)
The internal switching transistor is an n-channel power MOSFET. The RDS(on) of this internal power FET is approximately 0.25 ohm at +125_C. The 33394 has a nominal instantaneous current limit of 3.0 A (well below the saturation current of the MOSFET and external surface mounted inductor) in order to supply 1.2 A of current for the linear regulators that are connected to the VPRE pin (see Figure 1). The input to the drain of the internal N--channel MOSFET must be protected by an external series blocking diode, for reverse battery protection (see Figure 1).
4.2.2. Bootstrap Pin (BOOT)
An external bootstrap 0.1 F capacitor connected between SW1 and the BOOT pin is used to generate a high voltage supply for the high side driver circuit of the buck controller. The capacitor is pre charged to approximately 10V while the internal FET is off. On switching, the SW1 pin is pulled up to VBAT, causing the BOOT pin to rise to approximately VBAT+10V -- the highest voltage stress on the 33394.
4.2.3. External MOSFET Gate Drive (SW2G)
This is an output for driving an external FET for boost mode operation. Due to the fact that the gate drive supply voltage is VPRE the external power MOSFET should be a logic level device. It also has to have a low RDS(on) for acceptable efficiency. During buck mode, this gate output is held low.
4.2. Switching Regulator Functional Description
A block diagram of the internal switching regulator is shown in Figure 4. The switching regulator incorporates circuitry to implement a Buck or a Buck/Boost regulator with additional external components. A high voltage, low RDS(on) power MOSFET is included on chip to minimize the external components required to implement a Buck regulator. The power MOSFET is a sense FET to implement current limit. For low voltage operation, a low side driver is provided that is capable of driving external logic level MOSFETs. This allows a switching regulator utilizing Buck/Boost topology to be implemented. Two independent control schemes are utilized in the switching regulator. In Buck mode, voltage mode pulse-width modulation (PWM) control is used. The switcher output voltage divided by an internal resistor divider is sensed by an Error Amplifier and compared with the bandgap reference voltage. The PWM Comparator uses the output signal from the Error Amplifier as the threshold level. The PWM Comparator compares the sawtooth voltage from the Ramp Generator with the output signal from the Error Amplifier thus creating a PWM signal to the control logic block. The Error Amplifier inverting input and
4.2.4. Compensation (INV, VCOMP)
The PWM error amplifier inverting input and output are brought out to allow the loop to be compensated. The recommended compensation network is shown in Figure 18 and its Bode plot is in Figure 19. The use of external compensation components allows optimization of the buck converter control loop for the maximum bandwidth. Refer to the paragraph 5.2.3. Buck Converter Feedback Compensation in the Application Information section for further details of the buck controller compensation.
4.2.5. Switching Regulator Output Voltage (VPRE)
The output of the switching regulator is brought into the chip at the VPRE pin. This voltage is required for both the switching regulator control and as the supply voltage for all the linear regulators.
16
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Freescale Semiconductor, Inc. 33394
4.2.6. Switching Regulator Output Voltage Sense (VPRE_S)
This is the switching regulator output voltage sense input. The switcher output voltage VPRE is divided by an internal resistor divider and compared with the bandgap reference voltage (see Figure 4). Refer to Section 5 Application Information for detailed description of the switching regulator operation.
BOOT SW1 VBAT VPRE SOFT START SWITCHER MODE ENABLE Vbg CURRENT LIMIT BOOTSTRAP HS DRIVER VPRE BUCK & BOOST CONTROL LOGIC PWM COMP + - FEED FORWARD RAMP GENERATOR LS DRIVER VPRE SW2G VPRE_S 40 k E/A - + 11.7 k INV
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THERMAL LIMIT
Vbg 1.25 V
VCOMP Vbg
SWITCHER OSCILLATOR 200 kHz
Vbg
+ VPRE - COMP
Vbg 1.25 V + - Vbg 1.25 V
BOOST COMP
Figure 4. Switching Regulator Block Diagram
4.3. Voltage Regulator (VDDH)
The VDDH output is a linearly regulated +5.0 +/- 0.10V voltage supply capable of sourcing a maximum of 400 mA steady state current from VPRE (+5.6 V) for VBAT voltages from +4.0 V to +26.5 V (+45V transient). This regulator incorporates current limit short circuit protection and thermal shut down protection. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response, when choosing external components. See Table 1 in the Applications Information section for recommended output capacitor parameters.
NOTE :
Backfeeding into the VDDH output can cause problems during the power up sequence. Refer to the Electrical Characteristics VDDH Regulator Section for the maximum allowed backfed current into the VDDH output.
output, and incorporates current limit short circuit protection and over temperature shut down protection. This output is intended for FLASH memory programming and includes a dedicated enable pin (VPP_EN). The regulator enable can also be controlled through the SPI interface but requires both the VPP_EN pin and the SPI bit (EN_VPP bit) to be high to enable. The selection of tracking VDDH or VDD3_3 is controlled by the VPP_V bit in the SPI. Logic "1" selects VDDH (default), logic "0" selects VDD3_3. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. See Table 1 for recommended output capacitor parameters. The VPP tracking regulator should not be used in parallel with the VDDH regulator, because this arrangement can corrupt the proper power sequencing of the IC.
4.5. Tracking Voltage Regulator (VREFn)
The outputs of the VREF1, VREF2, VREF3 linear regulators are 100 mA at +5.0 V. They track the VDDH output. The power supplies are designed to supply power to sensors that are located external to the module. These regulators may be enabled or disabled via the SPI, which also provides fault reporting for these regulators. They are protected for short to 17
4.4. Tracking Voltage Regulator (VPP)
This linearly regulated +5.0 V/+3.3 V (SPI selectable) voltage supply is capable of sourcing 150 mA of steady state current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (up to +45V transient). It tracks the VDDH or VDD3_3
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battery (+18 V) and short to -2.0 V. Precautions must be taken to protect the VREF pins from exposure to transients. See Table 1 for recommended output capacitor parameters. Applications Information section for recommended output capacitor parameters.
NOTES: 4.5.1. VREF Over Temperature Latch Off Feature
If either the VREF1, VREF2 or VREF3 outputs is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150C to +190C. The output transistor remains off until the locally sensed temperature is 5C to 20C. below the trip off temperature. The output(s) will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If one of these outputs goes into over--temperature shutdown, it will not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). 1. The use of an EXTERNAL pass device allows the power dissipation of the 33394 to be reduced by approximately 50% and thereby allows the use of a thermally efficient package such as an HSOP 44 or QFN 44. The base drive control signal (VDDL_B) is provided by on chip circuitry. The regulated output voltage sense signal is fed back into the on chip differential amplifier through pin VDDL_FB. The collector of this external pass device should be connected to VPRE to minimize power dissipation and adequately supply 400 mA. Proper thermal mounting considerations must be accounted for in the PCB design. 2. Backfeeding into the VDDL output can cause problems during the power up sequence. Refer to the Electrical Characteristics VDDL Regulator Section for the maximum allowed backfed current into the VDDL output.
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4.6. Voltage Regulator (VDD3_3)
This linearly regulated +3.3 V +/-0.06 V voltage supply is capable of sourcing 120 mA of steady state current from VPRE (+5.6 V) for VBAT voltage from +4.0 V to +26.5 V (+45V transient). This regulator incorporates current limit short circuit protection and thermal protection. When no external pass transistor is used the VDD3_3 and the VDD3_3FB pins must be shorted together -- see Figure 22. The current capability of the VDD3_3 output can be increased by means of an external pass transistor -- see Figure 1. When the external pass transistor is used the VDD3_3 internal short circuit current limit does not provide the short circuit protection. The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. See Table 1 in the Applications Information section for recommended output capacitor parameters.
4.8. Keep-Alive/Standby Supply (VKAM)
This linearly regulated Keep Alive Memory voltage supply tracks the VDDL (+1.25 V to +3.3 V) core voltage, and is capable of sourcing 50 mA of steady state current from VPRE during normal microprocessor operation and 12 mA through KA_VBAT pin during stand-by/sleep mode. The VKAM regulator output incorporates a current limit short circuit protection. The output requires a specific range of capacitor values to be stable under all load/line conditions. See Table 1 in the Applications Information section for recommended output capacitor parameters.
NOTE :
The source current for the VKAM supply output depends on the sleep/wake state of the 33394.
4.9. Switched Battery Output (VSEN) NOTE :
Backfeeding into the VDD3_3 output can cause problems during the power up sequence. Refer to the Electrical Characteristics VDD3_3 Regulator Section for the maximum allowed backfed current into the VDD3_3 output. This is a saturated switch output, which tracks the VBAT and is capable of sourcing 125 mA of steady state current from VBAT. This regulator will track the voltage VBAT to less than 200 mV, and its output voltage is clamped at +17 V. The gate voltage of the internal N--channel MOSFET is provided by a charge pump from VBAT. There is an internal gate-to-source voltage clamp. This regulator is short circuit protected and has independent over--temperature protection. If this output is shorted and goes into thermal shutdown, the normal operation of all other voltage outputs is not impacted. This output is controlled by the SPI VSEN bit.
4.7. Voltage Regulator (VDDL)
The output voltage of the VDDL linear regulator is adjustable by means of an external resistor divider. This linearly regulated +/-2% core voltage supply uses an external pass transistor and is capable of sourcing 40 mA base drive current typically (see application circuit, Figure 1) of steady state current. The collector of the external NPN pass transistor is connected to VPRE (+5.6 V) for a VBAT voltage from +7.5 V to +26.5 V (+45V transient). The voltage output is stable under all load/line conditions. However, the designer must consider ripple and high frequency filtering as well as regulator response when choosing external components. Also, the dynamic load characteristics of the microprocessor, relative to CPU clock frequency changes must be considered. An additional external pass transistor, for VDDL regulation in the Boost mode, can be added between protected battery voltage (see Figure 1) and VDDL, with its base driven by VDDL_X. In that arrangement the 33394's core voltage supply operates over the whole input voltage range VBAT = +4.0 V to +26.5 V (up to +45V transient). See Table 1 in the
NOTE:
A short to VBAT on VREF1, VREF2, VREF3 or VSEN will not result in additional current being drawn from the battery under normal (+8 V to +18 V) voltage levels. Under jumpstart condition (VBAT = +26.5 V) and during load dump condition, the device will survive this condition, but additional current may be drawn from the battery.
4.9.1. VSEN Over Temperature Latch Off Feature
If the VSEN output is shorted to ground for any duration of time, an over temperature shut down circuit disables the output source transistor once the local die temperature exceeds +150C to +190C. The output transistor remains off until the locally sensed temperature drops 5C to 20C below
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the trip-off temperature. The output will periodically turn on and off until either the die temperature decreases or until the fault condition is removed. If the VSEN output goes into over--temperature shutdown, it does not impact the operation of any of the other outputs (assuming that no other package thermal or VPRE current limit specifications are violated). Fault information is reported through the SPI communication interface (see Figure 8). capacitor is used to program the timer. To minimize quiescent current during power down modes, the RC timer current should be drawn from one of the VDD supplies (see Figure 1). The threshold on the HRT pin has zero temperature coefficient and is set at 2.5 V.
4.12. Power Up/Down Sequencing
The 33394 power up sequence is specifically designed to meet the power up and power down requirements of the MPC565 microprocessor. The MPC565 processor requires that VDDH remain within 3.1 volts of VDDL during power up and can not lag VDDL by more than 0.5 volts. This condition is met by the 33394 regardless of load impedance. It is critical to note that the 33394 under normal conditions is designed to supply VKAM prior to the power up sequence on VDDH, VDD3_3 and VDDL. During power up and power down sequencing /PRERESET and /HRESET are held low. Power up and power down sequencing is implemented in six steps. During this process the reference voltage for VDDH, VDD3_3 and VDDL is ramped up in six steps. Minimum power up/down time is dependent on the internal clock and is 800 s. Maximum power up/down time is also dependent on load impedance. During the power up/down cycle, voltage level requirements for each step of VDDH, VDD3_3 and VDDL must be met before the supply may advance to the next voltage level. Hence VDDH and VDDL will remain within the 3.1/0.5 V window. Figure 6 illustrates a typical power up and down sequence.
4.10. Resets To Microprocessor
/PORESET - Power On Reset, /PRERESET -- Pre Reset, /HRESET- Hardware Reset. All the Reset pins are open drain `active low' outputs, capable of sinking 1.0 mA current and able to withstand +7.0 V. See Figure 1 and Figure 20 for recommended pull-up resistor values and their connection. The /PORESET pin is pulled up to the VKAM voltage by a pull up resistor. It is connected to the microprocessor Power On Reset (POR) pin, and is normally high. During initial battery connect the /PORESET is held to ground by the 33394. After the VKAM supply is in regulation and an internal 10 ms timer has expired, the /PORESET is released. If VKAM goes out of regulation the device will first pull the /PORESET and /PRERESET followed by a 0.7 s delay then /HRESET. By /HRESET low VDDH, VDD3_3 and VDDL will start a power down sequence. When the fault is removed a standard power up sequence is initiated. The VKAM linear regulator output must be out of regulation for greater than 20 s before /PORERSET and /PRERESET (with /HRESET 0.7 s delayed) are pulled low. If a fault occurs on VKAM in the Key-Off Mode (when the VIGN is off) and the fault is then removed the VKAM will regulate but /PORESET will not be released until Key-On (asserting VIGN pin) allows the 10 ms timer to run. The Reset signals (/PRERESET, /HRESET) are not asserted when the 33394 enters Sleep Mode by asserting the /SLEEP pin. When exiting out of Sleep Mode the 33394 asserts the Resets (/PRERESET, /HRESET) during the power up sequence. The /PRERESET and /HRESET pins are pulled up to the VKAM (see Figure 1) or to VDDL (see Figure 20). Refer to section 5. Application Information, paragraph 5.3. Selecting Pull-Up Resistors for detailed description of these two connection scenarios. The 33394 monitors the main supply voltages VDDH, VDD3_3 and VDDL. If any of these voltages falls out of regulation limits the /PRERESET will be pulled down followed by the /HRESET after 0.7 s delay, and the power down sequence will be initiated. There are several different scenarios how to connect the /PRERESET and /HRESET pins to the microprocessor. Typically the /PRERESET pin will be connected to the IRQ0 pin of the microprocessor, and the /HRESET to the microprocessor /HRESET pin (see Figure 5). The VDDH, VDD3_3 and VDDL linear regulator outputs must be out of regulation for greater than 20 s before /PRERESET (with /HRESET 0.7 s delayed) are pulled low.
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4.13. Regulator Enable Function (REGON)
This feature allows the microcontroller to select the delayed shut down of the 33394 device. It holds off the activation of the Reset signals, to the microcontroller, after the VIGN signal has transitioned and signals the request to shutdown the VDDH, VDD3_3, VDDL, VSEN and the VREFn supplies. This allows the microcontroller to delay a variable amount of time, after sensing that the VIGN signal has transitioned and signaled the request to shutdown the regulated supplies. This time can be used to store data to EPROM memory, schedule an orderly shutdown of peripherals, etc. The microcontroller can then drive the REGON signal, to the 33394, to the low logic state, to turn off the regulators (except for the VKAM supply).
4.14. Regulator Shutdown Function (/SLEEP)
This feature allows for an external control element (e.g. microprocessor) to shut down the 33394 regulators, even if the VIGN signal (or REGON) is active, by asserting the /SLEEP pin from high to low (falling edge transition). In this case the 33394 initiates the power down sequence, but the Reset signals (/PRERESET, /HRESET) are not asserted. This allows the microprocessor to continue to execute code when it is supplied only from the Keep Alive supply VKAM. When the microprocessor exits sleep state by pulling /SLEEP pin high the Resets (/PRERESET, /HRESET) are asserted during the power up sequence. The /SLEEP pin has an internal pull down, therefore when its functionality is not used this pin can be either pulled up to VKAM, VBAT, pulled down to ground or left open. The /SLEEP pin should not be pulled up to VDDH.
4.11. Hardware Reset Timer (HRT)
The HRT pin is used to set the delay between VDDH, VDD3_3 and VDDL active and stable and the release of the /HRESET and /PRERESET outputs. An external resistor and
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33394 Output
VDDH VDD3_3 VDDL VIGN * VDD3_3 = 3.3V (not used by MPC56x) VDDH = 5.0V VDD3_3 = 3.3V* VDDL = 2.6V 2 4 3 6 VKAM = 2.6V VKAM /PORESET 10ms /PRERESET 5 /HRESET 0.7ms HRESET HRT DELAY HRT DELAY 0.7ms HRT DELAY 0.7ms 2.6V IRQ0 1 2.6V 2.6V 7 11 8 9 10 KAPWR, VDDSRAM1,2,3 VDDRTC PORESET
MPC56X Supply Input
VDDH, VDDA, VFLASH5 5.0V
NVDDL, QVDDL, VDD, VDDSYN, 2.6V VDDF
Freescale Semiconductor, Inc...
Figure 5. 33394 Timing Diagram 1 Module connected to the battery, VKAM starts to regulate, /PORESET is released after VKAM is in regulation for 10 ms. 2 VIGN is applied, 33394 starts power up sequence. 3 VDDH, VDD3_3, VDDL are stable and in regulation before /PRERESET and /HRESET are released (with a HRT delay programmable by an external capacitor and resistor, HRT pin). 4 Any of VDDH, VDD3_3, VDDL voltages out of regulation initiate /PRERESET asserted. Power down sequence initiated. 5 /HRESET is asserted 0.7 ms after /PRERESET 6 When fault is removed and VDDH, VDD3_3, VDDL are in regulation, the /PRERESET and /HRESET outputs are released (with an HRT delay). 7 When VKAM goes out of regulation limits (4% below its nominal value), /PORESET, /PRERESET and /HRESET (/HRESET with 0.7 ms delay) are asserted - see Note 1. 8 33394 initiates power down sequence. 9 Fault on VKAM removed, the 33394 initiates the start up sequence. 10 When VDDH, VDD3_3, VDDL are in regulation again, the /PRERESET and /HRESET outputs are released (with an HRT delay). 11 /PORESET is released with a 10 ms delay after the fault on VKAM was removed.
VDDH = 5.0 V VDD3_3 = 3.3 V LESS THAN 3.1 V VDDL = 2.6 V*
0V
POWER UP SEQUENCE
POWER DOWN SEQUENCE
*NOTE: VDDL = 2.6 V for MPC565
Figure 6. 33394 Power Up/Down Sequence
* VKAM voltage level for MPC55x devices is 3.3 V and for MPC56x devices is 2.6 V.
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4.15. SPI Interface to Microcontroller (Serial Peripheral Interface)
The pins specified for this function are: DI (Data Input), DO (Data Output), CS (Chip Select) and SCLK. Refer to Figure 3 for the 33394 SPI timing information. The delay, which is needed from CS leading edge active to the first SCLK leading edge transition (0 to 1) is approximately 125 ns. The SCLK rate is a maximum of 5.0 MHz. The SPI function will provide control of such 33394 features as VREFn regulator turn on/off, VREFn fault reporting and CAN wake up feature activation. Refer to Figure 7 & Figure 8 for the data and status bit assignments for the 16 bit SPI data word exchange. pin be in a logic low state whenever the chip select pin (CS) makes any transition. For this reason, it is recommended though not necessary, that the SCLK pin is commanded to a low logic state as long as the device is not accessed (CS in logic low state). When CS is in a logic low state, any signal at the SCLK and DI pin is ignored and the DO is tri--stated (high impedance).
4.15.3. DI (Data Input) Pin
The DI pin is used for serial data input. This information is latched into the input register on the rising edge of SCLK. A logic high state present on DI will program a specific function (see Figure 7 for the data bits assignments for the 16 bit SPI data word exchange.). The change will happen with the falling edge of the CS signal. To program the specific function of the 33394 a 16 bit serial stream of data is required to be entered into the DI pin starting with LSB. For each rising edge of the SCLK while CS is logic high, a data bit instruction is loaded into the shift register per the data bit DI state. The shift register is full after 16 bits of information have been entered. To preserve data integrity, care should be taken to not transition DI as SCLK transitions from a low to high logic state.
4.15.1. CS (Chip Select) Pin
The system MCU selects the 33394 to be communicated with through the use of the CS pin. Whenever the pin is in a logic high state, data can be transferred from the MCU to the 33394 and vice versa. Clocked--in data from the MCU is transferred to the 33394 shift register and latched in on the falling edge of the CS signal. On the rising edge of the CS signal, output status information is transferred from the output status register into the device's shift register. Whenever the CS pin goes to a logic high state, the DO pin output is enabled allowing information to be transferred from the 33394 to the MCU. To avoid any spurious data, it is essential that the transition of the CS signal occur only when SCLK is in a logic low state.
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4.15.4. DO (Data Output) Pin
The serial output (DO) pin is the output from the shift register. The DO pin remains tri--state until the CS pin goes to a logic high state. See Figure 8 for the status bits assignments for the 16-bit SPI data word exchange. The CS positive transition will make LSB status available on DO pin. Each successive positive SCLK will make the next bit status available. The DI/DO shifting of data follows a first--in--first--out protocol with both input and output words transferring the Least Significant Bit (LSB) first.
4.15.2. SCLK (System Clock) Pin
The shift clock pin (SCLK) clocks the internal shift registers of the 33394. The serial input (DI) data is latched into the input shift register on the rising edge of the SCLK. The serial output pin (DO) shifts data information out of the shift register also on the rising edge of the SCLK signal. It is essential that the SCLK
33394 SPI Registers:
Serial Input Data/Control
Default Value Bit Name 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8
Bit Definitions: Bit 15 to 8 = 0
Default Value Bit Name 1 7 WKUP 1 6 CAN_EN 1 5 VPP_V 1 4 EN_VPP 1 3 VSEN 1 2 VREF3 1 1 VREF2 1 0 (LSB) VREF1
Bit Definitions: Bit 7 -- WKUP: WAKEUP activation. WKUP = 1: WAKEUP pin will signal CAN bus activity Bit 6 -- CAN_EN: Enables CAN receiver, will draw small current during power off Bit 5 -- VPP_V: Set VPP reference to 5V (1) or 3.3V (0), default is 5V Bit 4 -- EN_VPP: - Used to turn the VPP regulator off and on from the MCU Bit 3 -- VSEN: - Used to turn the VSEN regulator off and on from the MCU Bit 2 -- VREF3: - Used to turn the VREF3 regulator off and on from the MCU Bit 1 -- VREF2: - Used to turn the VREF2 regulator off and on from the MCU Bit 0 -- VREF1: - Used to turn the VREF1 regulator off and on from the MCU Figure 7. SPI Input Data/ Control Register
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33394 SPI Registers:
Serial Output Data/Status
Default Value Bit Name 0 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8
Bit Definitions: Bit 15 to 8 = 0
Default Value Bit Name 0 7 VSEN-T 0 6 VREF3-T 0 5 VREF2-T 0 4 VREF1-T 0 3 VSEN-I 0 2 VREF3-I 0 1 VREF2-I 0 0 (LSB) VREF1-I
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Bit Definitions: Bit 7 -- VSEN-T: - Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 6 -- VREF3-T: - Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 5 -- VREF2-T: - Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 4 -- VREF1-T: - Will be set (1), if a thermal limit occurred since last SPI data transfer Bit 3 -- VSEN-I: - Will be set (1), if a current limit condition exists Bit 2 -- VREF3-I: - Will be set (1), if a current limit condition exists Bit 1 -- VREF2-I: - Will be set (1), if a current limit condition exists Bit 0 -- VREF1-I: - Will be set (1), if a current limit condition exists NOTES: # individual thermal limit latch will clear on the trailing edge of the SPI CS signal Figure 8. SPI Output Data/ Status Register
4.16. CAN Transceiver
The CAN protocol is defined in terms of 'dominant' and 'recessive' bits. When the digital input (CANTXD) is a logic "0" (negated level, dominant bit), CANH goes to +3.5 V (nominal) and CANL goes to +1.5 V (nominal). The digital output will also be negated. When the digital input is logic "1" (asserted level, recessive bit), CANH and CANL are set to +2.5 V (nominal). The corresponding digital output is also asserted.
4.16.1. CAN Network Topology
There are two 120 (only two), terminations between the CANH and CANL outputs. The majority of the time, the module
controller will contain one of the terminations. The other termination should be as close to the other "end" of the CAN Bus as possible. The termination provides a total of 60 differential resistive impedance for generation of the voltage difference between CANH and CANL. Current flows out of CANH, through the termination, and then through CANL and back to ground. The CAN bus is not defined in terms of the bus capacitance. A filter capacitor of 220 pF to 470 pF may be required. The maximum capacitive load on the CAN bus is then 15 nF (not a lumped capacitance but distributed through the network cabling). Refer to Figure 9.
PCM CANH
120
Common Mode Choke 2.2 mH 470 pF*
Max : 31 Remotes
470 pF*
Vehicle Term.
W
470 pF* 470 pF*
120
W
CANL
*Optional
Figure 9. CAN Load Characteristics
4.16.2. CAN Transceiver Functional Description
A block diagram of the CAN transceiver is shown in Figure 10. A summary of the network topology is shown in Figure 9. The transceiver has wake up capability controlled by the state of the SPI bit WKUP. This allows 33394 to enter a low power mode and be awakened by CAN bus activity. When activity is
sensed on the CAN bus pins, the 33394 will perform a power up sequence and will provide the microprocessor with indication (WAKEUP pin high) that wake up occurred from a CAN message. The 33394 may be placed back in low quiescent mode by pulling the /SLEEP pin from high to low.
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The Wake-up function can be disabled through SPI by setting the WKUP bit to 0. The CAN transceiver of the 33394 is designed for communications speeds up to 1.0 Mbps. The use of a common mode choke may be required in some applications. When the 33394 CAN transceiver physical interface is not used in the system design, the CAN bus driver pins CANH and CANL should be shorted together. input drives the outputs to a differential (dominant) voltage, where the CANH output is +3.5 V and the CANL output is +1.5 V. A logic `1' input drives the outputs to their idle (recessive) state, where the CANH and CANL outputs are +2.5 V. An internal pull-up to VDDH shall guarantee a logic "1" input level if this input is left open. On power-up, or in the event of a thermal shutdown, this input must be toggled high and then low to clear the thermal fault latch. The faulted CAN bus output(s) will remain disabled until the thermal fault latch is cleared. The CAN bus data rate is determined by the data rate of CANTXD.
4.16.3. CANH
CANH is an output driver stage that sources current on the CANH output. It's output follows CANL, but in the opposite polarity. The output is short circuit protected. In the event that battery or ground is lost to the module, the CANH transmitter's output stage is disabled.
4.16.6. CANRXD
This is a CMOS compatible output used to send data from the CAN bus pins, CANH and CANL, to the microprocessor. When the voltage differential between CANH and CANL is under the differential input voltage threshold (recessive state), CANRXD is logic `1'. When the voltage differential between CANH and CANL is over the voltage threshold (dominant state), CANRXD is logic `0'. In standby mode, input voltage threshold remains the same. There is a minimum of 0.1 V of hysteresis between the high and low (and vice versa) transition points.
4.16.4. CANL
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CANL is an output driver stage that sinks current on the CANL output. The sink type output is short circuit protected. In the event that battery or ground is lost to the module, the CANL transmitter's output stage is disabled.
4.16.5. CANTXD
CANTXD input comes from the microcontroller and drives that state of the CAN bus pins, CANH and CANL. A logic `0'
OverTemp Sense & Hysteresis
VDDH VDDH CAN_EN CANTXD 10 A 0.8 - 2.0 V 25 kW 0.5 - 1.0 V + - CANRXD AWAKE CAN_EN 5 kW 5 kW 25 kW Complimentary High/Low Side Drivers w/ Current Limit CANH CANL
CANRXD
+ -
2.5 V
Figure 10. CAN Transceiver Block Diagram
4.16.7. CAN Over Temperature Latch Off Feature
If the CANH or CANL output is shorted to ground or battery for any duration of time, an over temperature shut down circuit disables the output stage. The output stage remains latched off until the CANTXD input is toggled from a logic '1' to a logic '0' to clear the over temperature shutdown latch. Thermal shutdown does not impact the remaining functionality of the IC.
on the module level in Figure 11. The nomenclature is suited to a test environment. In the application, a loss of ground condition results in all I/O pins floating to battery voltage. In this condition, the CAN bus must not source enough current to corrupt the bus.
4.16.9. CAN Loss of Assembly Battery
The loss of battery condition at the IC level is that the power input pins of the IC see infinite impedance to the battery supply voltage (depending upon the application) but there is some undefined impedance looking from these pins to ground. In this condition, the CAN bus must not sink enough current to corrupt the bus. Refer to Figure 12.
4.16.8. CAN Loss of Assembly Ground
The definition of a loss of ground condition at the device level is that all pins of the IC (excluding transmitter outputs) will see very low impedance to VBAT. The loss of ground is shown
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Battery 16 V VBAT 51 CANH ICANL CANL 51 ICANH Battery VBAT CANH ICANL CANL ICANH
W
VIGN
W
VIGN
POWER OAK
68 43 43
+ -2V - 68 43 43
POWER OAK
+ +6V -
W W W
VDDH + VDD3_3 VDDL GND -2V -
W W W
VDDH + VDD3_3 VDDL GND +6V -
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Figure 11. CAN Loss of Ground Test Circuit
Figure 12. CAN Loss of Battery Test Circuit
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5. APPLICATION INFORMATION
This section provides information on external components that are required by the 33394. The IC is designed to operate in an automotive environment. Conducted immunity and radiated emissions requirements have been addressed during the design. However, the IC requires some external protection. Protection is required for all pins connected directly to battery. The module designer should use an MOV or another transient voltage suppressor in all cases, when the load dump transition exceeds + 45 volts with respect to ground. Protection should also include a reverse battery protection diode (or relay) and input filter. This is required to protect the 33394 from ESD and +/- 300V ignition transients. Typical configurations are shown in Figure 1. Outputs and inputs connected directly to connector pins require module level ESD protection. reasonable for most of practical applications. Then the ESR of the output capacitor has to satisfy the following condition: ESR Where: Vo is the maximum allowed linear regulator voltage drop caused by the load current transient. Io is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. In this example the VDDH output with the 400 mA load step is considered with the maximum voltage drop of 100mV. This gives the output capacitor's maximum ESR value of: ESR
v DVoo DI
+ 100 mV + 250 mW 400 mA
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5.1. Selecting Components for Linear Regulators
The output capacitor of the linear regulator serves two different purposes. It maintains the linear regulator loop stability, and it provides an energy reservoir to supply current during very fast load transients. This is especially true when supplying highly modulated loads like microcontrollers and other high-speed digital circuits. Due to the limited bandwidth of the linear regulators, the output capacitor is selected to limit the ripple voltage caused by these abrupt changes in the load current. During the fast load current transients, the linear regulator output capacitor alone controls the initial output voltage deviation. Hence, the output capacitor's equivalent series resistance (ESR) is the most critical parameter. The outputs, which do not experience such severe conditions (the VREF e.g.), use the output capacitor mainly for stability purpose, and therefore its capacitance value can be significantly smaller. The typical output capacitor parameters are: C = 1.0 F; ESR = 2.0 ohms. When a ceramic 1 F capacitor is used, the ESR can be provided by a discrete serial resistor (see Figure 20). The following example shows how to determine the output capacitance for a heavily loaded output supplying digital circuits.
This level of ESR requires a relatively large capacitance. In order to maintain the linear regulator stability and to satisfy large load current steps requirements the solid tantalum capacitor 100F/10V with ESR = 200 m. One device that meets these requirements is the TPSC107K010S020 tantalum capacitor from the AVX Corporation.
DVESR + ESR
DIo + 200
mW
400 mA
+ 80 mV
mV
In the next step, the voltage drop associated with the capacitance can be calculated: A5 DVC + DIo C Dt + 0.4100 mF ms + 20 Where: C is the output capacitance.
Dt is the linear regulator response time.
Io is the maximum current transient, which can occur due to the abrupt step in the linear regulator load current. Assuming that the capacitor ESL is negligible, the total voltage drop in the voltage regulator output caused by the current fast transient can be calculated as:
DVtotal + DVESR ) DVC + 80
mV
) 20 mV + 100 mV
5.1.1. Selecting the Output Capacitor Example:
The output capacitance must be selected to provide sufficiently low ESR. The selected capacitor must have an adequate voltage, temperature and ripple current rating for the particular application. In order to calculate the proper output capacitor parameters, several assumptions will be made. 1) During the very fast load current transients, the linear regulator can not supply the required current fast enough, and therefore for a certain time the entire load current is supplied by the output capacitor. 2) The capacitor's equivalent series inductance (ESL) is neglected. These assumptions can greatly simplify the calculations, and are
A ceramic capacitor with capacitance value 10nF should be placed in parallel to provide filtering for the high frequency transients caused by the switching regulator. Properly sized decoupling ceramic capacitor close to the microprocessor supply pin should be used as well. Table 1 shows the suggested output capacitors for the 33394 IC linear regulator outputs. Other factors to consider when selecting output capacitors include key off timing for memory retention. Though the VKAM is not a heavily loaded output, the VKAM output capacitor has to have a sufficiently large capacitance value to supply current to the microcontroller for a certain time after battery voltage is disconnected.
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Table 1. Linear Regulator Output Capacitor Examples
Output Value/Rating VDDH VPP VDD3_3 VDDL VREFx VKAM* 100uF/10V 33uF/10V 68uF/6.3V 100uF/6.3V 10uF/16V 100uF/6.3V TPSC107K010S0200 TPSB336K010S0650 TPSC686K006S0200 TPSC107K006S0150 THJB106K016S TPSC107K006S0150 SMD tantalum Part n. (AVX Corp.)
5.2. Switching Regulator Operation
The 33394 switching regulator circuit consists of two basic switching converter topologies. One is the typical voltage mode PWM step-down or buck regulator, which provides pre-regulated VPRE voltage (+5.6 V) during normal operating conditions. During cold start-up, when the car battery is weak, the input voltage for the 33394 can fall below the lower operating limit of the step-down converter. Under such conditions, the step-up or boost converter provides the required value of the VPRE voltage. The following paragraphs describe the basic principles of the two converters operation.
inductor input voltage is clamped one forward diode drop below ground. The inductor current during the off time is: iL(off) Where: toff is the off-time of the power switch. iL(off) is the inductor current during the off time. Vfwrd is forward voltage drop across the rectifier. During the steady state operation iL(on) = iL(off) = IL, and Vin/Vo = d Where: d is the duty cycle, and d = ton/T. T is switching period, T = 1/f. f is the frequency of operation. Two relations give the ripple voltage in the output capacitor Co. The first describes ripple voltage caused by current variation upon the output capacitance Co: f The other is caused by current variations over the output capacitor equivalent series resistance ESR: VppESR DIL RESR Practically, the ESR contributes predominantly to the buck converter ripple voltage: VppESR >>VppCo The inductor peak current can be calculated as follows: IpkL Where: Io is the average output current. VppCo
+ (Vo * Vfwd) L
toff
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Buck Mode
One switching cycle of the step-down converter operation has two distinct parts: the power switch on state and the off state. When the power switch is on, one inductor terminal is connected to the input voltage Vin, and the other inductor terminal is the output voltage Vo. During this part of the switching period the rectifier (catch diode) is back biased, and the current ramps up through the inductor to the output: iL(on) Where: ton is the on-time of the power switch. Vin is the input voltage. Vo is the output voltage. iL(on) is the inductor current during the on-time. L is the inductance of the inductor L. During the on time, current ramping through the inductor stores energy in the inductor core. During the off time of the power switch, the input voltage source Vin is disconnected from the circuit. The energy stored in the core forces current to continue to flow in the same direction, the rectifier is forward biased and the
+
(Vin
* Vo)
L
ton
DI + 8Co L
+
+ Io ) 1 DIL 2
26
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Freescale Semiconductor, Inc. 33394
IQ Q ID Vin D IL L + CO - VO RLOAD
DIL
+ IL IO
IQ
L
ILO +
+ ILOAD Vout - VD Vfwd -ID RLOAD
Vin POWER SWITCH ON
CO
Freescale Semiconductor, Inc...
ILO + VD(fwd) CO Vout
+ ILOAD
RLOAD
VCo ton T toff t
POWER SWITCH OFF
-
Figure 13. Basic Buck Converter Operation and its Waveforms
Boost Mode
The operation of the boost converter also consists of two parts, when the power switch is on and off. When the power switch turns on, the input voltage source is placed directly across the inductor, and the current ramps up linearly through the inductor as described by: iL(on) Where: ton is the on-time of the power switch. Vin is the input voltage. iL(on) is the inductor current during the on-time. L is the inductance of the inductor L. The current ramping across the inductor stores energy within the core material. In order to maintain steady-state operation, the amount of energy stored during each switching cycle, times the frequency of operation must be higher (to cover the losses) than the power demands of the load: Psto Where: Where:
iL(off)
in + (Vo * VL )
toff
toff is the off-time of the power switch. Vo is the output voltage. During the steady state operation iL(on) = iL(off) = IL, and d
+ Vin L ton
* + Vo VoVin
d is the duty cycle, and d = ton/T. T is switching period, T = 1/f. f is the frequency of operation. The ripple voltage of the boost converter can be described as: VppCo Where: VppCo is the ripple caused by output current. The portion of the output ripple voltage caused by the ESR of the output capacitor is: VppESR I + Coo (Vo
+ 1 LI pk f u Pout 2
2
* Vin)
f
Vo
When the power switch turns off again, the inductor voltage flies back above the input voltage and is clamped by the forward biased rectifier at the output voltage. The current ramps down through the inductor to the output until the new on time begins or, in case of discontinuous mode of operation, until the energy stored in the inductor core drops to zero.
+ (Io
Vo Vin
) 1 DIL) 2
RESR
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Freescale Semiconductor, Inc. 33394
Where Io is the average output current. The inductor peak current is given by the following equation:
IL L Q Vin IQ ID D + CO - VO RLOAD
IpkL
+ Io
Vo Vin
) 1 DIL 2
DIL
+ IL
ID IO +
+
ILOAD
IQ RLOAD
Freescale Semiconductor, Inc...
ION Vin
L Vout
CO -
POWER SWITCH ON
VQ
IL IOFF VIN POWER SWITCH OFF Vout + CO
+ ILOAD
RLOAD
VCo ton T toff t
-
Figure 14. Basic Boost Converter Operation and its Waveforms
5.2.1. Switching Regulator Component Selection
The selection of the external inductor L2 and capacitor C2 values (see Figure 15) is a compromise between the two modes of operation of the switching regulator, the pre regulated voltage VPRE and the dropout voltage of the linear regulators. Ideal equations describing the peak--peak inductor current ripple, peak--peak output voltage ripple and peak inductor current are shown below. Since the switching regulator will work mostly in the buck mode, the inductor and the switcher input and output capacitor were selected for optimum buck controller performance, but also taking into account the restriction placed by adopting the boost converter as well.
IQ Q1 VRDS(on) RDS(on) D1 Vin VRL RL Vfwd1 IL L Vfwd2 D2 ESR Q2 + CO -
5.6 V and the linear regulators require a minimum of 0.4 V dropout voltage. This leaves a 0.2 V window for the peak--to-peak output voltage ripple. Assuming the following conditions: Vin(typ) = 13.5 V Io = 1.2 VPRE = 5.6 V (+6 V in the boost mode) f = 200 kHz Vfwd1 = Vfwd2 = 0.5 V Maximum allowed output voltage ripple in the buck mode Vpp(max) = 0.2 V/2 = 0.1 V (to allow for process and temperature variations).
+ RLOAD VO
5.2.1.1. Selecting the Inductor
In order to select the proper inductance value, the inductor ripple current IL has to be determined. The usual ratio of IL to output current Io is: IL = 0.3 Io As described in the previous section, and taking into account the 33394 switcher topology (see Figure 15), the inductor ripple current can be estimated as:
Figure 15. 33394 Switcher Topology The following example shows a procedure for determining the component values. The VPRE output is set to regulate to
DIL +
(Vin
* Vo * Vfwd2)
L
Vo Vfwd2 Vin f
)
28
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Freescale Semiconductor, Inc. 33394
After substitution, the calculated inductance value is L = 45 H, which gives 47 H standard component value. The peak-to peak ripple current value is: IL = 0.345 A. The peak inductor current is given by: ILpk = 0.5IL + Io = 0.5x0.345 + 1.2 = 1.37[A] The inductor saturation current is given by the upper value of the 33394 internal switch current limit Ilim(max) = 3.0 A. Considering also the inductor serial resistance, these requirements are met, for example by the PO250.473T inductor from Pulse Engineering, Inc. VppESR = IL x RESR = 0.345 x 0.08 = 28 [mV] One device that meets both, the low ESR, and the temperature stability requirements is, for example, the TPSV107K020R0085 tantalum capacitor from AVX Corp.
Boost Converter Power Capability
The boost converter with selected components has to be able to deliver the required power. Due to the nature of this non-compensated PFM control technique, the Boost converter output ripple voltage is higher than if it utilized a typical PWM control method. Therefore the switcher output voltage level is set higher than in the Buck mode (in the Boost mode VPRE = +6 V), in order to maintain a sufficient dropout voltage for the 5-volt linear regulators (VDDH, VREFs) and to avoid unwanted Resets to the microcontroller. The most stringent conditions for the 33394 boost converter occur with the lowest input voltage: Vin(min) = 3.5 V Io = 0.8 A Vpre = +6 V f = 200 kHz Vfwd1 = Vfwd2 = 0.5 V d = 0.75, duty cycle is fixed at 75% in boost mode
5.2.1.2. Selecting the Catch Diode D1
The rectifier D1 current capability has to be greater than calculated average current value. The maximum reverse voltage stress placed upon this rectifier D1 is given by maximum input voltage (maximum transient battery voltage). These requirements are met, for example by the HSM350 (3 A, 50 V) schottky diode from Microsemi, Inc.
Freescale Semiconductor, Inc...
5.2.1.3. Selecting the Output Capacitor
The output capacitor Co should be a low ESR part, therefore the 100 F tantalum capacitor with 80 m ESR was chosen. From the formula for calculating the ripple voltage:
VRES RD IL L IQ Vfwd2 D2 ESR Q2 Vin + CO - VO +
IL ILIM I01 I02 RLOAD L1 > L2 DIL1 < DIL2 IO1 > IO2 T
IL1 IL2
t
Figure 16. 33394 Switcher Topology - Boost Mode The input voltage drop associated with the resistance of the internal switch Q1 and inductor series resistance can be estimated as: VD Where: VD is the voltage dissipated on the major parasitic resistances, RDSon of the internal power switch and inductor series resistance RL. For the worst case conditions: RD = RDSon(max) + RL = 0.25 + 0.1 = 0.35[] Ipk(min) is the minimum internal power switch current limit value. Then the equation for calculating IL can be modified as follows: Then the maximum average input current can be calculated as: IinAve
[ Ipk(min)
RD
+ 2.5 A
0.35
W + 0.875
V
+ Ipk(min) * 1 DIL + 2.5 * 0.125 + 2.43[A] 2 2
h u Pout
Finally, the boost converter power capability has to be higher than the required output power or: Pin(max)
Where Pin(max) is the boost converter maximum input power: h is the boost converter efficiency, in our case h is estimated to be h = 85%, and includes switching losses of the external power switch Q2 (MOSFET) inductor and capacitors AC losses, and output rectifier D2 (schottky) switching losses. Pout is the boost converter output power, which includes power loss of the output rectifier D2: Pout
+ 3.5 * 0.875 47 10 *6 + 125[mA]
DIL + Vin * VD L
) Vfwd2) * (Vin * VD)] d + (Vo ) Vfwd2) f [(6 ) 0.5) * (3.5 * 0.875)] 0.75 (6 ) 0.5) 0.2 10
[(Vo
6
+ (Vo ) Vfwd2) Io + (6 ) 0.5) 0.8 + 5.2[W] Pin + (Vin * VD) IinAve h + + (3.5 * 0.875) 2.43 0.85 + 5.42[W]
As can be seen, the boost converter input power capability meets the required criteria.
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5.2.1.4. Selecting the Power MOSFET Q2
The boost converter maximum output voltage plus the voltage drop across the output schottky rectifier D2 gives the MOSFET's maximum drain-source voltage stress: BVdsQ2>Vo+Vfwd2 = 6 V+0.5 V, as can be seen, the breakdown voltage parameter is not critical. The more important in our case is the Q2 current handling capability. The external power MOSFET has to withstand higher currents than the upper current limit of the 33394: IDQ2>3A In order to keep the power dissipation of the 33394 boost converter to its minimum, a very low RDSon power MOSFET has to be selected. Moreover, due to the fact that the 33394 external MOSFET gate driver is supplied from VPRE, in order to assure proper switching of Q2 a logic level device has to be selected. Last but not least, the Q2 package has to suitable for the harsh automotive environment with low thermal resistance. These requirements are met, for example by the MTD20N03HDL power MOSFET from ON Semiconductor.
5.2.2. Input Filter Selection
Since the switcher will work in the Boost mode only during cold crank condition, the 33394 EMC (electromagnetic compatibility) performance is not of concern during this mode of operation. Therefore, only the Buck mode of operation is important for selecting the appropriate input filter. For the Buck converter topology (see Figure 13) the low impedance 3rd order filter (C3, L2, C4 and C26 in the Application Schematic Diagram Figure 20) offers a good solution. It can be seen from the Buck converter current waveforms that comparatively high current pulses are drawn from the converter's input source. The filter inductance must be kept minimal and the capacitor, which is placed right next to the power switch, must be sized large enough to provide sufficient energy reservoir for proper switcher operation. The ESR of this input capacitor combination C4, C26 has to be sufficiently low to reduce the switching ripple of the switcher input node VBAT. There are three main reasons to keep the voltage ripple of the VBAT pin at its minimum. First, it is the EMC (electromagnetic compatibility) performance of the switcher in the normal operating mode (buck mode). Second, it allows a smooth transition between the boost and buck mode of operation. Third, it helps to avoid entering an undervoltage condition too early. A practical way to achieve sufficiently low ESR of the switcher input capacitor, even at low temperature extremes, is to use several high value ceramic capacitors in parallel with a large electrolytic capacitor. These capacitors should be physically placed as close to the VBAT pins as possible.
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5.2.1.5. Selecting the Boost Converter Output Rectifier D2
Criteria similar to that of selecting the power MOSFET was used to select the boost converter output rectifier. Its reverse breakdown voltage is not a critical parameter: VrD2>Vo=6 V The D2 rectifier has to withstand higher peak current than is the 33394 internal switch upper current limit Ilim(max). The most important parameter is its forward voltage drop, which has to be minimal. This parameter is also crucial for the proper 33394 switcher functionality, and especially for proper transition between the buck and boost modes. Finally, its switching speed, forward and reverse recovery parameters play a significant role when selecting the output rectifier D2. These requirements are met, for example by the HSM350 schottky rectifier from Microsemi, Inc.
5.2.3. Buck Converter Feedback Compensation
A typical control loop of the buck regulator is shown in Figure 17. The loop consists of a power processing block -- the modulator in series with an error-detecting block -- the Error (Feedback) Amplifier. In principle, a portion of the output voltage (VPRE of the 33394 switcher) is compared to a reference voltage (Vbg) in the Error Amplifier and the difference is amplified and inverted and used as a control input for the modulator to keep the controlled variable (output voltage VPRE) constant.
Vin Gain Block (Modulator) Vin + Ramp Vout - + PWM Signal
+
MODULATOR
Vout To Load
S
G -
H Feedback Block Vout/Vin = G/(1 + GH) Zf - + Reference Voltage ERROR FEEDBACK AMPLIFIER Zin
Figure 17. The Buck Converter Control Loop
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Freescale Semiconductor, Inc. 33394
R2 C3 C1 GAIN (dB) - E/A + R Ref VCOMP U1 40 20 0 -20 MODULATOR fZ1 A1 fZ2 Ifxo A2 ERROR AMPLIFIER C2 80 CLOSED LOOP (overall) 60 R3 VPRE_S R1 fp(LC) fp1 fp2
Figure 18. Error Amplifier Two-Pole-Two-Zero Compensation Network The process of determining the right compensation components starts with analysis of the open loop (modulator) transfer function, which has to be determined and plotted into the Bode plot (see Figure 19). The modulator DC gain can be determined as follows:
-40 -60 1 90 MODULATOR 0 PHASE (deg) 10 100 1000 f (Hz)
fZ(ESR) 10 k 100 k 1M
Freescale Semiconductor, Inc...
ADC
Vin + DVe
Where Ve is the maximum change of the Error Amplifier voltage to change the duty cycle from 0 to 100 percent (Ve = 2.6 V at Vbat =14 V). As can be seen from Figure 19, the buck converter modulator transfer function has a double complex pole caused by the output L-C filter. Its corner frequency can be calculated as: fp(LC) o This double pole exhibits a --40dB per decade rolloff and a --180 degree phase shift. Another point of interest in the modulator's transfer function is the zero caused by the ESR of the output capacitor Co and the capacitance of the output capacitor itself: fz(ESR) 1 + 2pRESRCo
-90 ERROR AMPLIFIER
-180
+ 2p 1LC
-270 -360 1 10 100 CLOSED LOOP (overall) 1000 f (Hz) 10 k 100 k 1M
Figure 19. Bode Plot of the Buck Regulator The frequency of the compensating poles and zeros can be calculated from the following expressions:
The ESR zero causes +20dB per decade gain increase, and +90 degree phase shift. Once the open loop transfer function is determined, the appropriate compensation can be applied in order to obtain the required closed loop cross over frequency and phase margin (~60 degree) -- refer to Figure 18 and Figure 19. Figure 19 shows the 33394 Switching Regulator modulator gain-phase plot, E/A gain-phase plot, closed loop gain-phase plot, and the E/A compensation circuit. The frequency fxo is the required cross-over frequency of the buck regulator. In order to achieve the best performance (the highest bandwidth) and stability of the voltage-mode controlled buck PWM regulator the two-pole-two-zero type of compensation was selected -- see Figure 19 for the compensated Error Amplifier Bode plot, and Figure 18 for the compensation network. The two compensating zeros and their positive phase shift (2 x +90 degree) associated with this type of compensation can counteract the negative phase shift caused by the double pole of the modulator's output filter.
+ 2pR12C2 1 fz2 + [ 2pR11C3 2p(R1 ) R3)C3 1 fp1 + 2pR3C3 C ) C2 fp2 + 1 [1
fz1 2pR2C1C2 2pR2C1
and the required absolute gain is:
R1R3 R3 Refer to Application Schematic Diagram (Figure 20) and Table 2 for the 33394 switcher component values.
A2
+ R2 R1 + R2(R1 ) R3) [ R2
A1
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Table 2.
Part number (Figure 18) R1 R2 R3 C1 C2 C3 Application diagram part number (Figure 1) 33394 internal resistor R2 R1 C6 C7 C5 Component value 39.6k 100k 430 100pF 1.0nF 3.3nF
Where R is the HRT timer pull-up resistor, C is the HRT timer capacitor VB is the pull-up voltage, Vth is the HRT timer threshold voltage (Vth = 2.5V nominal value), VSAT is the saturation voltage of the internal pull-down transistor. If the HRT timer pull-up resistor is connected to VDDH (see Figure 1) and the resistor value is 47 kW, therefore the VSAT can be neglected, the formula for calculating the time delay can be simplified to: tD
5.3. Selecting Pull-Up Resistors
All the Resets (/PORESET, /PRERESET and /HRESET) are open drain outputs, which can sink a maximum of 1 mA drain current. This determines the pull-up resistor minimum value. VKAM should be used as the pull-up source for the /PORESET output. /PORESET is pulled low only during initial battery connect or when VKAM is below 2.5 volts (for VDDL = 2.6 V). To select the /PRERESET and /HRESET pull-up resistor connections, consider current draw during sleep modes. For example, the pull up resistor on /PRERESET and /HRESET should receive its source from VDDL, if the sleep mode or low power mode of the module is initiated primarily by the state of the VIGN pin. Refer to Figure 20 for recommended pull-up resistor values. Another way to connect the /PRERESET and /HRESET pull-up resistors is to connect them to the VKAM output together with the /PORESET pull-up resistor (see Figure 1). This is the preferable solution when the sleep or low power mode is initiated primarily by the microprocessor. In that case, when the 33394 is shut down by pulling the /SLEEP pin down, all three Resets (/PORESET, /PRERESET and /HRESET) stay high. Since they are pulled-up to the supply voltage (VKAM) they draw no current from the VKAM and the module quiescent current is minimized.
+ 0.7
RC
5.5. Selecting the VKAM Resistor Divider
The VKAM linear regulator output voltage is divided by an external resistor divider and compared with the bandgap reference voltage (Vbg) in the input of the VKAM error amplifier. The resistor divider can be designed according to the following formula: VKAM VKAMref = 1.267 V Where VKAMref is the bandgap reference voltage. Since the VKAM feedback pin (VKAM_FB) input current is only a few nA, the resistor value can be selected sufficiently high in order to minimize the quiescent current of the module. See Figure 20 for the VKAM resistor divider recommended values.
Freescale Semiconductor, Inc...
+ VKAMref
1
) Rupper Rlower
5.6. Selecting the VDDL Resistor Divider
The VDDL regulator resistor divider is designed according to the same formula as described in the paragraph above (see Figure 20). VDDL
5.4. Selecting Hardware Reset Timer Components
The HRT input sets the delay time from VDDH, VDD3_3 and VDDL stable to the release of /PRERESET and /HRESET. When sizing the delay time the module design engineer must consider capacitor leakage, printed board leakage and HRT pin leakage. Resistor selection should be low enough to make the leakage currents negligible. The Hardware Reset (/HRESET) delay can be calculated as follows: Delay time: tD
+ VDDLref
1
) Rupper Rlower
Where VDDLref = 1.267 V Nonetheless, the actual resistor values should be chosen several decades lower than in the previous example. This is due to the fact that the VDDL linear regulator needs to be pre-loaded by a minimum of 10 mA current in order to guarantee stable operation. See Figure 20 for the VDDL resistor divider recommended values.
+ *RC
ln[
(VB VSAT) Vth ] (VB VSAT)
*
*
*
32
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Freescale Semiconductor, Inc. 33394
JP1 1 2 +Battery VDDH C3 1.0uF/50V SW1 DIP-2 C29 1.0uF/50V VIGN C28 VKAM 10nF + C23 10nF C24 22uF R4 22k 1.0uF/50V C26 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 U1 VBAT VBAT VBAT VBAT VBAT KA_VBAT N/C VIGN VKAM VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB N/C /PRERESET /HRESET /PORESET CANRXD CANTXD SW1 SW1 SW1 SW1 SW1 N/C BOOT SW2G GND INV VCOMP VPRE VPRE_S VDDH VREF2 VREF3 N/C DO SCLK DI CS N/C /SLEEP HRT CANH CANL GND 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 C1 100nF BOOT C6 100pF R22 100k VPRE C30 10nF VPRE_S C10 47uF 37 36 35 34 /SLEEP VDDH + C11 10nF C7 1.0nF C4 100uF/35V D2 * MURS320T3 Q3 1 L2 6.8uH 2 + + C2 D3 SS25 R13 18R R14 4.7k Q1 MMSF3300R2 C5 100uF/16V 3.3nF R1 430R Vbat 1 L1 47uH D1 20BQ030 2
VPP_EN IGN R3 4.7k
R6 20k VSEN REGON WAKEUP VPP_EN
MC33394DWB
VREF1 C8 10nF C9 1.0uF R19 2.0R
VDDL_X VDDL_B VDDL_FB
VREF2 C14 1.0uF R20 2.0R CANH C15 10nF
Freescale Semiconductor, Inc...
VPP + C12 10nF +3.3V C21 10nF 37 36 35 34 R9 4.7k R10 4.7k R11 4.7k R12 4.7k DO SCLK DI VKAM CS + C22 10uF C13 10uF
CANRXD CANTXD
CANL
VREF3 R15 47k C18 1.0uF C16 1.0uF R21 2.0R C17 10nF
/PRERESET
/PORESET
/HRESET
R8 120R
VDDH
C25 * R16 10k R17 10k R18 10k
C27 *
Q3 VPRE Q2 MJD31C VDDL = 2.6V VDDL R5 110R VDDL_FB C20 47uF R7 100R VDDL_B Q3 MJD31C
VDDL_X
+Battery GND +Battery GND +Battery GND +Battery GND VKAM /SLEEP VPP WAKEUP VSEN IGN +3.3V REGON /PORESET /PRERESET CANH /HRESET CANL CANRXD VREF2 CANTXD VREF1 CS VREF3 DI VPP_EN SCLK VDDH DO VDDL GND
+ C15 10nF
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted. Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Table 3. 33394 Evaluation Board Performance
Parameter Value (TA = 25_C, Vin = 14V) V Load [mV] [mA] 5.028 5.026 5.023 5.022 5.021 3.307 2.667 2.638 400 150 100 100 100 120 400 60 Line Regulation (Vin = 5.2V to 26.5V) Load Regulation (Vin = 14 V)
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CON/34
J1
Figure 20. 33394 Application Circuit Schematic Diagram
DV
[mV] 10 10 8 8 6 5 5 2
Load [mA] 400 150 100 100 100 120 400 60
DV
[mV] 18 5 8 10 11 7 10 14
Load [mA] 0 to 400 0 to 150 0 to 100 0 to 100 0 to 100 0 to 120 0 to 400 0 to 60
VDDH VPP VREF1 VREF2 VREF3 VDD3_3 VDDL VKAM
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Table 4. 33394DWB Evaluation Board Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 Qty. 1 1 3 1 1 1 1 10 4 2 1 1 1 2 1 1 1 1 1 1 1 1 2 1 1 6 1 1 1 1 1 1 1 3 3 1 1 1 C1 C2 C3,C26,C29 C4 C5 C6 C7 C8,C11,C12,C15,C17,C19,C21,C23,C28,C30 C9,C14,C16,C18 C20,C10 C13 C22 C24 C25,C27 D1 D2 D3 JP1 J1 L1 L2 Q1 Q2,Q3 R1 R2 R3,R9,R10,R11,R12,R14 R4 R5 R6 R7 R8 R13 R15 R16,R17,R18 R19,R20,R21 SW1 TP1 U1 Part Designator Value/ Rating 100nF/16V, Ceramic X7R 100F/20V 1.0F/50V 100F/35V 3.3nF, Ceramic X7R 100pF, Ceramic X7R 1.0nF, Ceramic X7R 10nF, Ceramic X7R 1.0F, Ceramic X7R 47F/10V, Tantalum 10F/16V, Tantalum 10F/6.3V, Tantalum 22F/6.3V, Tantalum 470pF, Ceramic X7R 30V/2A Schottky 200V/3A Diode 50V/2A Schottky 2-pin, 0.2 (5.1mm) 34-pin, 0.1 x 0.1 47H 6.8H 30V/11.5A, Mosfet 100V/3A, BJT 430R, Resistor 0805 100k, Resistor 0805 4.7k, Resistor 0805 22k, Resistor 0805, 1% 110R, Resistor 0805, 1% 20k, Resistor 0805, 1% 100R, Resistor 0805, 1% 120R, Resistor 0805 18R, Resistor 0805 47k, Resistor 0805 10k, Resistor 0805 2.0R, Resistor 0805 2-Position DIP Switch Test Point, 0.038 Integrated Circuit Part Number/ Manufacturer Any manufacturer TPSV107K020R0085, AVX Corp. C1812C105K5RACTR, Kemet UUB1V101MNR1GS, Nichicon Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer TPSC476K010R0350, AVX Corp. TPSB106K016R0800, AVX Corp. TPSA106K006R1500, AVX Corp. TPSA226K006R0900, AVX Corp. Any manufacturer 20BQ030, International Rectifier MURS320T3, ON Semiconductor SS25, General Semiconductor Terminal Block PCB Header Connector P0250.473T, Pulse Engineering P0751.682T, Pulse Engineering MMSF3300R2, ON Semiconductor MJD31C, ON Semiconductor Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer BD02, C&K Components 240-333, Farnell 33394DWB/ Motorola
Freescale Semiconductor, Inc...
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
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Freescale Semiconductor, Inc. 33394
JP1 1 2
+BATTERY
VDDH
* D2
Q4 1
L2 6.8
1.0 50 V
SW1 DIP-2
mF/
C29 R14
MURS320T3 1.0
mF/50 V
mH
2
C3
100 35 V
mF/
+
C4
VBAT 1.0 50 V
mF/
1 C26 C1 100 nF
L1
D1 20BQ030 2 C5 3.3 nF Q1 MTD20N03HDL R1 430R
VPRE_S
47 D3 SS25 R13 18R
mH
C2 100 20 V
mF/
+
OPTIONAL OUTPUT FILTER L3 1 2
33
mF/16 V
C30
+
VPP_EN
4.7k R3 4.7 k C28 10 nF
VIGN 2.6V VKAM C23 10 nF
+
VKAM VIGN KA_VBAT VBAT VBAT SW1 SW1 SW1 BOOT SW2G GND
C24 100
mF
R4 22 k
12 13 14 15 16 17 18 19 20 21 22
11 10 9 8 7 6 5 4 3 2 1
U1 C6 100 pF C7 1.0 nF VPRE VDDH C10 47 VREF2 C14 1.0 R15 VDDH 47 k C18 1.0
C27 *
R6 20 k
5.0V @ 100mA VREF1 C8 10 nF C9 1.0
+
Freescale Semiconductor, Inc...
mF
5.0V @ 150mA VPP C12 10 nF
VDDL_FB /PRERESET /HRESET /PORESET CANRXD CANTXD GND CANL CANH HRT /SLEEP
VKAM_FB VSEN REGON WAKEUP VREF1 VPP_EN PC33394FC VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B
INV VCOMP VPRE VPRE_S VDDH VREF2 VREF3 DO SCLK DI CS
44 43 42 41 40 39 38 37 36 35 34
R2 100 k
5.0V @ 400 mA
mF
+
C11 10 nF
5.0V @ 100 mA
+
C13 33 VPRE
mF
mF
+
Q2 MJD31C +3.3V C21 10 nF
23 24 25 26 27 28 29 30 31 32 33
C15 10 nF
120R
R19 10R
+
VKAM R9 R10 R11 R12
R16 10 k 4.7 k 4.7 k 4.7 k 4.7 k
R17 10 k DO
R18 10 k
C25 *
mF
VREF3 C16 1.0 5.0V @ 100 mA
C22 47 mF
37 36 35 34
SCLK DI CS 2.6V @ 400 mA VDDL C19 10 nF
mF
+
C17 10 nF Q4
VPRE Q3 MJD31C VDDL_B
Q4 MJD31C
VDDL_X
+BATTERY GND +BATTERY GND +BATTERY GND +BATTERY GND VKAM /SLEEP VPP WAKEUP VSEN IGN +3.3V REGON /PDRESET /PRERESET CANH /HRESET CANL CANRXD VREF2 CANTXD VREF1 CS VREF3 DI VPP_EN SCLK VDDH DO VDDL GND
VDDL
+
C20 100
mF
R5 110R VDDL_FB R7 100R
J1
*Notes: 1. D2 is a protection diode against reverse battery fault condition. In those applications, which do not require this type of protection, diode D2 can be ommitted. Notes: 2. Capacitors C25, C27 are optional and may be used for CAN tranceiver evaluation.
Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CON/34
Figure 21. 33394 Application Circuit with Increased 3.3V Output Current Capability
For More Information On This Product,
35
Freescale Semiconductor, Inc. 33394
Table 5. 33394FC Evaluation Board Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 Qty. 1 1 3 1 1 1 1 9 1 3 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1 3 1 1 6 1 1 1 1 1 1 1 3 1 1 1 1 C1 C2 C3,C26,C29 C4 C5 C6 C7 C8,C11,C12,C15,C17,C19,C21,C23,C28 C18 C9,C14,C16 C10,C22 C13 C20 C24 C27,C25 C30 D1 D2 D3 JP1 J1 L1 L2 L3 Q1 Q2,Q3,Q4 R1 R2 R3,R9,R10,R11,R12,R14 R4 R5 R6 R7 R8 R13 R15 R16,R17,R18 R19 SW1 TP1 U1 Part Designator Value/ Rating 100nF/16V, Ceramic X7R 100F/20V 1.0F/50V 100F/35V 1.5nF, Ceramic X7R 100pF, Ceramic X7R 1.0nF, Ceramic X7R 10nF, Ceramic X7R 1.0F, Ceramic X7R 1.0F/35V Tantalum 47F/10V Tantalum 33F/10V Tantalum 100F/6.3V Tantalum 22F/6.3V, Tantalum 470pF, Ceramic X7R 33F/16V 30V/ 2A Schottky 200V/3A Diode SS25 2-pin, 0.2 (5.1mm) 34-pin, 0.1 x 0.1 47H 6.8H Ferrite Bead 30V/20A Mosfet 100V/3A BJT 680R, Resistor 0805 100k, Resistor 0805 4.7k, Resistor 0805 22k, Resistor 0805, 1% 110R, Resistor 0805, 1% 20k, Resistor 0805, 1% 100R, Resistor 0805, 1% 120R, Resistor 0805 18R, Resistor 0805 47k, Resistor 0805 10k, Resistor 0805 10R, Resistor 0805 2-Position DIP Switch Test Point Integrated Circuit Part Number/ Manufacturer Any manufacturer TPSV107K020R0085, AVX Corp. C1812C105K5RACTR, Kemet UUB1V101MNR1GS, Nichicon Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer TPSA105K035R3000, AVX Corp. TPSC476K010R0350, AVX Corp. TPSB336K010R0500, AVX Corp. TPSC107K006R0150, AVX Corp. TPSA226K006R0900, AVX Corp. Any manufacturer TPSC336K016R0300, AVX Corp. 20BQ030, International Rectifier MURS320T3, ON Semiconductor SS25, General Semiconductor Terminal Block PCB Header Connector P0250.473T, Pulse Engineering P0751.682T, Pulse Engineering HF30ACC575032/ TDK MTD20N03HDL, ON Semiconductor MJD31C, ON Semiconductor Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer Any manufacturer BD02, C&K Components 240-333, Farnell MC33394DWB/ Motorola
Freescale Semiconductor, Inc...
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41
36
For More Information On This Product, Go to: www.freescale.com INTEGRATED CIRCUIT DEVICE DATA MOTOROLA ANALOG
Freescale Semiconductor, Inc. 33394
Input voltage +7V to +26.5V ON OFF S1 R5 4.7k C1 100F + 1 2 3 C5 10nF 4 5 6 R2 22k 7 8 9 VREF1 = 5V @ 100mA + C8 10nF C9 1.0F VPP = 5V @ 150mA + C16 10nF C17 47F VDDH 11 12 3.3V @ 120mA + C11 47F 14 15 Q1 MJD44H11 VDDL = 2.6V @ 600mA + C12 10nF C13 100F R4 22R /PRERESET R3 20R /HRESET 16 17 18 19 13 10 VBAT VBAT KA_VBAT VIGN VKAM VKAM_FB VSEN REGON WAKEUP SW1 SW1 SW1 BOOT SW2G GND INV VCOMP VPRE 44 43 42 41 330nF 40 39 38 37 36 35 34 33 VREF2 = 5V @ 100mA + 32 VREF3 = 5V @ 100mA C18 1.0F + 31 C20 C21 10nF 1.0F 30 29 28 27 26 25 /PORESET CANRXD CANTXD CANH CANL GND 24 23 60R Rt 47k VDDH Ct 1.0 F VDDH = 5V @ 400mA + C14 100F C19 10nF C15 10nF Cb 100nF BAV99 D1 MBRS340T C2 100F L1 47F VPRE = 5.6V +
VKAM = 2.6V @ 60mA + C6 10nF C7 47F
Cf3 3.3nF
Rf2 100k Cf1 100pF
Rf3 430R
R1 20k
Cf2 1nF
PC33394
VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB /PRERESET /HRESET
VPRE_S VDDH VREF2 VREF3 DO SCLK DI CS /SLEEP HRT
Freescale Semiconductor, Inc...
C10 10nF VPRE
/PORESET 20 R6 10k VKAM R7 10k R8 10k 21 22
Figure 22. 33394 Buck-Only Application
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For More Information On This Product,
37
Freescale Semiconductor, Inc. 33394
+12V @ 100mA + D3 C23 47F Input voltage +10V to +26.5V ON OFF S1 R5 4.7k C1 100F + 1 2 3 C5 10nF 4 5 6 R2 22k 7 8 9 VREF1 = 5V @ 100mA VBAT VBAT KA_VBAT VIGN VKAM VKAM_FB VSEN REGON WAKEUP SW1 SW1 SW1 BOOT SW2G GND INV VCOMP VPRE 44 43 T1 42 41 40 39 38 37 36 35 34 33 VREF2 = 5V @ 100mA + 32 VREF3 = 5V @ 100mA C18 1.0F + 31 C20 C21 10nF 1.0F 30 29 28 27 26 25 24 23 60R Rt 47k VDDH Ct 1.0 F VDDH = 5V @ 400mA + C14 100F C19 10nF C15 10nF Cf3 3.3nF Rf2 100k Cf1 100pF Cb 100nF D1 MBRS340T Rf3 430R C2 100F + D3 + C22 47F
-12V @ 100mA VPRE = 5.6V
VKAM = 2.6V @ 60mA + C6 10nF C7 47F
R1 20k
Cf2 1nF
Freescale Semiconductor, Inc...
10 VDDH 11 12 3.3V @ 120mA + C11 47F 14 15 Q1 MJD31C 16 17 13
PC33394
+ C8 10nF C9 1.0F VPP = 5V @ 150mA + C16 10nF C17 47F
VREF1 VPP_EN VPP VDD3_3 VDD3_3FB VDDL_X VDDL_B VDDL_FB /PRERESET /HRESET /PORESET CANRXD CANTXD
VPRE_S VDDH VREF2 VREF3 DO SCLK DI CS /SLEEP HRT CANH CANL GND
C10 10nF VPRE
VDDL = 2.6V @ 400mA + C12 10nF C13 100F R4 22R /PRERESET R3 20R /HRESET
18 19
/PORESET 20 R6 10k VKAM R7 10k R8 10k 21 22
Figure 23. 33394 Flyback Converter Provides Symmetrical Voltages
38
For More Information On This Product, Go to: www.freescale.com INTEGRATED CIRCUIT DEVICE DATA MOTOROLA ANALOG
Freescale Semiconductor, Inc. 33394
PACKAGE DIMENSIONS
DH SUFFIX 44-LEAD HSOP PLASTIC PACKAGE CASE 1291-01 ISSUE O
PIN ONE ID
h
X 45 _
E3 E2
4X
E5
1
44
D 0.325
Freescale Semiconductor, Inc...
22
23
B
EXPOSED HEATSINK AREA
E1
22X
E bbb Y A A2
M
A CB H
DATUM PLANE
E4 BOTTOM VIEW
NOTES: 1. CONTROLLING DIMENSION: MILLIMETER. 2. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.150 PER SIDE. DIMENSIONS D AND E1 DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE TIEBAR PROTRUSIONS. ALLOWABLE TIEBAR PROTRUSIONS ARE 0.150 PER SIDE. MILLIMETERS MIN MAX 3.000 3.400 0.025 0.125 2.900 3.100 15.800 16.000 11.700 12.600 0.900 1.100 --- 1.000 13.950 14.450 10.900 11.100 2.500 2.700 6.400 7.300 2.700 2.900 --- 1.000 0.840 1.100 0.350 BSC 0.220 0.350 0.220 0.320 0.230 0.320 0.230 0.280 0.650 BSC --- 0.800 q 0_ 8_ aaa 0.200 bbb 0.100 DIM A A1 A2 D D1 D2 D3 E E1 E2 E3 E4 E5 L L1 b b1 c c1 e h
D2
42X
e
D3 c C
SEATING PLANE
GAUGE PLANE
SECTION W-W L1 W L (1.600) DETAIL Y W A1
bbb C
q
Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
CCCC EEE CCCC EEE CCCC
b1
c1
b
aaa
M
CA
D1
4X
39
Freescale Semiconductor, Inc. 33394
PACKAGE DIMENSIONS
FC SUFFIX 44-LEAD QFN PLASTIC PACKAGE CASE 1310-01 ISSUE D
PIN 1 INDEX AREA
0.1 C
2X
A 0.1 C
2X
9
M G 1.0 1.00 0.8 0.75 0.1 C 0.05 C (0.325) (0.65) DETAIL G 5
9 0.05 0.00
C
SEATING PLANE
Freescale Semiconductor, Inc...
VIEW ROTATED 90 CLOCKWISE
M B 0.1 C A B 6.85 6.55
34 44
DETAIL M PIN 1 IDENTIFIER EXPOSED DIE ATTACH PAD
1
33
6.85 6.55 0.1 C A B 0.65
23 11
40X
NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. THE COMPLETE JEDEC DESIGNATOR FOR THIS PACKAGE IS: HF-PQFP-N. 4. CORNER CHAMFER MAY NOT BE PRESENT. DIMENSIONS OF OPTIONAL FEATURES ARE FOR REFERENCE ONLY. 5. COPLANARITY APPLIES TO LEADS, CORNER LEADS AND DIE ATTACH PAD. 6. FOR ANVIL SINGULATED QFN PACKAGES, MAXIMUM DRAFT ANGLE IS 12.
44X
0.75 0.50
22
12
N
44X
0.37 0.23 0.1 0.05
M M
VIEW M-M
CAB C
(45 )
(3.53)
0.60 0.24 0.60 0.24 DETAIL N
CORNER CONFIGURATION OPTION
44X
0.065 0.015
(0.25) DETAIL N
PREFERRED CORNER CONFIGURATION
4
DETAIL T
4 3.4 3.3 0.475 0.425
2X 0.39 0.31 BACKSIDE PIN 1 INDEX
(90 )
R 0.25 0.15 DETAIL M
PREFERRED BACKSIDE PIN 1 INDEX
2X
0.1 0.0
DETAIL M
BACKSIDE PIN 1 INDEX OPTION
DETAIL T
PREFERRED BACKSIDE PIN 1 INDEX
40
For More Information On This Product, Go to: www.freescale.com INTEGRATED CIRCUIT DEVICE DATA MOTOROLA ANALOG
Freescale Semiconductor, Inc. 33394
PACKAGE DIMENSIONS
DWB SUFFIX 54-LEAD SOICW-EP PLASTIC PACKAGE CASE 1377-01 ISSUE B 10.3 5 7.6 7.4 C 9 B 2.65 2.35
52X 1 54 NOTES: 1. ALL DIMENSIONS ARE IN MILLIMETERS. 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 3. DATUMS B AND C TO BE DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 4. THIS DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 5. THIS DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THIS DIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY. 6. THIS DIMENSION DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 MM. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM. 7. EXACT SHAPE OF EACH CORNER IS OPTIONAL. 8. THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.1 MM AND 0.3 MM FROM THE LEAD TIP. 9. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM. THIS DIMENSION IS DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY.
0.65
PIN 1 INDEX
Freescale Semiconductor, Inc...
4 9 B B 18.0 17.8 C L
27
28
5.15
2X 27 TIPS
A
54X
SEATING PLANE
0.3
ABC
0.10 A
A R0.08 MIN C A 8 0 0.9 0.5 SECTION B-B 0.1 0.0 C 0.25
GAUGE PLANE
0 MIN
(1.43)
6.6 5.9 0.30 A B C
(0.29) 0.30 0.25
BASE METAL
4.8 4.3 0.30 A B C
6
SECTION A-A ROTATED 90_ CLOCKWISE VIEW C-C
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For More Information On This Product,
EEEE CCCC EEEE CCCC EEEE CCCC
0.38 0.22
M
(0.25)
PLATING
0.13
A BC
8
41
Freescale Semiconductor, Inc. 33394 NOTES
Freescale Semiconductor, Inc...
42
For More Information On This Product, Go to: www.freescale.com INTEGRATED CIRCUIT DEVICE DATA MOTOROLA ANALOG
Freescale Semiconductor, Inc. 33394 NOTES
Freescale Semiconductor, Inc...
Go to: www.freescale.com MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
43
Freescale Semiconductor, Inc. 33394
Freescale Semiconductor, Inc...
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. MOTOROLA and the logo are registered in the US Patent & Trademark Office. All other product or service names are the property of their respective owners.
E Motorola, Inc. 2001.
How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3-20-1, Minami-Azabu. Minato-ku, Tokyo 106-8573 Japan. 81-3-3440-3569 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre, 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. 852-26668334 Technical Information Center: 1-800-521-6274 HOME PAGE: http://www.motorola.com/semiconductors/
44
For More Information On This Product, Go to: www.freescale.com INTEGRATED CIRCUIT DEVICE DATA MOTOROLA ANALOG MC33394/D

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